Patents by Inventor Hideki Mizuhara
Hideki Mizuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11107915Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.Type: GrantFiled: December 17, 2020Date of Patent: August 31, 2021Assignee: NUVOTON TECHNOLOGY CORPORATION JAPANInventors: Chie Fujioka, Hiroshi Yoshida, Yoshihiro Matsushima, Hideki Mizuhara, Masao Hamasaki, Mitsuaki Sakamoto
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Publication number: 20210104629Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.Type: ApplicationFiled: December 17, 2020Publication date: April 8, 2021Inventors: Chie FUJIOKA, Hiroshi YOSHIDA, Yoshihiro MATSUSHIMA, Hideki MIZUHARA, Masao HAMASAKI, Mitsuaki SAKAMOTO
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Patent number: 10903359Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.Type: GrantFiled: January 17, 2019Date of Patent: January 26, 2021Assignee: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.Inventors: Chie Fujioka, Hiroshi Yoshida, Yoshihiro Matsushima, Hideki Mizuhara, Masao Hamasaki, Mitsuaki Sakamoto
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Publication number: 20200395479Abstract: A semiconductor device includes: a semiconductor layer that includes principal surfaces; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, is thicker than the semiconductor layer, and comprises a first metal material; a metal layer that includes principal surfaces, is disposed with the principal surface in contact with the principal surface, and comprises a metal material having a Young's modulus greater than that of the first metal material; and transistors. The transistor includes a source electrode and a gate electrode on a side facing the principal surface. The transistor includes a source electrode and a gate electrode on a side facing the principal surface.Type: ApplicationFiled: January 17, 2019Publication date: December 17, 2020Inventors: Chie FUJIOKA, Hiroshi YOSHIDA, Yoshihiro MATSUSHIMA, Hideki MIZUHARA, Masao HAMASAKI, Mitsuaki SAKAMOTO
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Compound semiconductor device, method for producing same, and resin-sealed type semiconductor device
Patent number: 10553676Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.Type: GrantFiled: January 10, 2019Date of Patent: February 4, 2020Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hideki Mizuhara, Yoshihiro Matsushima, Shinichi Oohashi -
COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SAME, AND RESIN-SEALED TYPE SEMICONDUCTOR DEVICE
Publication number: 20190165098Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.Type: ApplicationFiled: January 10, 2019Publication date: May 30, 2019Inventors: Hideki MIZUHARA, Yoshihiro MATSUSHIMA, Shinichi OOHASHI -
Compound semiconductor device, method for producing same, and resin-sealed type semiconductor device
Patent number: 10224397Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.Type: GrantFiled: November 27, 2017Date of Patent: March 5, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Hideki Mizuhara, Yoshihiro Matsushima, Shinichi Oohashi -
COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SAME, AND RESIN-SEALED TYPE SEMICONDUCTOR DEVICE
Publication number: 20180083100Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.Type: ApplicationFiled: November 27, 2017Publication date: March 22, 2018Inventors: Hideki MIZUHARA, Yoshihiro MATSUSHIMA, Shinichi OOHASHI -
Compound semiconductor device, method for producing same, and resin-sealed type semiconductor device
Patent number: 9865679Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.Type: GrantFiled: October 12, 2015Date of Patent: January 9, 2018Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Hideki Mizuhara, Yoshihiro Matsushima, Shinichi Oohashi -
COMPOUND SEMICONDUCTOR DEVICE, METHOD FOR PRODUCING SAME, AND RESIN-SEALED TYPE SEMICONDUCTOR DEVICE
Publication number: 20160035828Abstract: In a semiconductor element having a compound semiconductor layer epitaxially grown on a silicon substrate, an object is to suppress generation of deficiency or problems of reliability deriving from the ends of the element that are generated when dividing into semiconductor devices by dicing. A compound semiconductor layer epitaxially grown on a silicon substrate is formed via a buffer layer made of aluminum nitride. In the periphery of the semiconductor device, a scribe lane is present to surround a semiconductor element region. Along the scribe lane, the aluminum nitride layer is covered with a coating film for protection against humidity and moisture.Type: ApplicationFiled: October 12, 2015Publication date: February 4, 2016Inventors: HIDEKI MIZUHARA, YOSHIHIRO MATSUSHIMA, SHINICHI OOHASHI -
Patent number: 8378229Abstract: A circuit board includes a substrate made principally of metal. An opening is provided on the substrate. A first wiring layer is provided on one surface of the substrate via a first insulating layer, and a second wiring layer is provided on the other surface of the substrate via a second insulating layer. A conductor penetrates the substrate via the opening and connects the first wiring layer with the second wiring layer. An end of the opening at one surface side of the substrate has a tapering form on a surface layer thereof, and the first insulating layer has a recess on an upper surface thereof in an upper region of the opening.Type: GrantFiled: June 11, 2010Date of Patent: February 19, 2013Assignee: Sanyo Electric Co., Ltd.Inventors: Mayumi Nakasato, Hideki Mizuhara
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Patent number: 8344522Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 ?m.Type: GrantFiled: March 18, 2009Date of Patent: January 1, 2013Assignee: Sanyo Electric Co., Ltd.Inventors: Hideki Mizuhara, Hajime Kobayashi, Toshiya Shimizu
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Patent number: 8338946Abstract: An electrode for a semiconductor device is formed on the mounting surface (particularly, the outer periphery thereof) of a semiconductor substrate in a semiconductor module. In order to secure a large gap between the electrodes, an insulating layer is formed on the electrode. Also formed are a plurality of bumps penetrating the insulating layer and connected to the electrode, and a rewiring pattern integrally formed with the bumps. The rewiring pattern includes a bump area and a wiring area extending contiguously with the bump area. The insulating layer is formed to have a concave upper surface in an interval between the bumps, and the wiring area of the rewiring pattern is formed to fit that upper surface. The wiring area of the rewiring pattern is formed to be depressed toward the semiconductor substrate in relation to the bump area of the rewiring pattern.Type: GrantFiled: December 6, 2010Date of Patent: December 25, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Yasuyuki Yanase, Yoshio Okayama, Kiyoshi Shibata, Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Tetsuya Yamamoto, Masurao Yoshii
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Patent number: 8283681Abstract: A lighting device including a metal substrate to prevent temperature rise of LED chip is offered. The lighting device includes the metal substrate, an anode or cathode electrode of the LED chip disposed on the metal substrate, brazing materials connecting the LED chip and the metal substrate, and a groove formed in the anode or cathode electrode. Forming the groove can prevent an occurrence of a crack in the brazing materials. Also, a lighting device includes the metal substrate, an anode and cathode electrode of the LED chip disposed on the metal substrate and brazing materials connecting the LED chip and the metal substrate. Further, a slit is formed in the metal substrate between the anode and cathode electrode. Forming the slit in the metal substrate can prevent an occurrence of a crack in the brazing materials.Type: GrantFiled: October 15, 2010Date of Patent: October 9, 2012Assignees: SANYO Electric Co., Ltd., SANYO Semiconductor Co., Ltd.Inventors: Noriaki Sakamoto, Naoki Tanahashi, Tsuyoshi Hasegawa, Takaya Kusabe, Masahiko Mizutani, Hideki Mizuhara, Yoshinari Sakuma
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Patent number: 8183090Abstract: To reduce connection defects between a circuit substrate provided on a core substrate and a circuit to be mounted thereon, thereby improving reliability as a multilayered device mounting substrate. The device mounting substrate includes: a first circuit substrate composed of a substrate, an insulating layer formed on this substrate, and a first conductive layer (including conductive parts) formed on this insulating layer; and a second circuit substrate mounted on the first circuit substrate, being composed of a base, a second conductive layer (including conductive parts) formed on the bottom of the base, and a third conductive layer (including conductive parts) formed on the top of the base. Here, the first and second circuit substrates are bonded by pressure so that the first and second conductive parts are laminated and embedded together into the insulating layer.Type: GrantFiled: August 13, 2010Date of Patent: May 22, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Mayumi Nakasato, Hideki Mizuhara, Takaya Kusabe, Sadamichi Takakusaki
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Patent number: 8093699Abstract: A circuit device in which highly reliable sealing with a resin can be achieved is provided. A semiconductor chip is provided on one surface of an insulating resin film and a conductive layer that is electrically connected to the semiconductor chip is provided on another surface of the insulating resin film. A solder ball (electrode) for the connection to a circuit board is provided on the conductive layer. An insulating resin layer is further provided between the conductive layer and the circuit board to embed the electrode therein. In this manner, the circuit device is formed. A side face of the semiconductor chip is covered with the insulating resin film.Type: GrantFiled: December 22, 2005Date of Patent: January 10, 2012Assignee: Sanyo Electric Co., Ltd.Inventors: Yasuhiro Kohara, Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
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Publication number: 20110263121Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.Type: ApplicationFiled: April 27, 2011Publication date: October 27, 2011Applicant: Sanyo Electric Co., Ltd.Inventors: Ryosuke Usui, Hideki Mizuhara, Takeshi Nakamura
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Publication number: 20110241025Abstract: A lighting device including a metal substrate to prevent temperature rise of LED chip is offered. The lighting device includes the metal substrate, an anode or cathode electrode of the LED chip disposed on the metal substrate, brazing materials connecting the LED chip and the metal substrate, and a groove formed in the anode or cathode electrode. Forming the groove can prevent an occurrence of a crack in the brazing materials. Also, a lighting device includes the metal substrate, an anode and cathode electrode of the LED chip disposed on the metal substrate and brazing materials connecting the LED chip and the metal substrate. Further, a slit is formed in the metal substrate between the anode and cathode electrode. Forming the slit in the metal substrate can prevent an occurrence of a crack in the brazing materials.Type: ApplicationFiled: October 15, 2010Publication date: October 6, 2011Applicants: SANYO ELECTRIC CO., LTD., SANYO SEMICONDUCTOR CO., LTD.Inventors: Noriaki SAKAMOTO, Naoki Tanahashi, Tsuyoshi Hasegawa, Takaya Kusabe, Masahiko Mizutani, Hideki Mizuhara, Yoshinari Sakuma
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Patent number: 8022533Abstract: Circuit elements including a plurality of semiconductor devices and passive elements embedded in an insulating resin film are formed on a metal substrate having a surface roughness Ra of 0.3 to 10 ?m. This produces an anchoring effect occurs between the substrate and the insulating film, thereby improving the adhesiveness between the substrate and the insulating resin film.Type: GrantFiled: June 29, 2005Date of Patent: September 20, 2011Assignee: Sanyo Electric Co., Ltd.Inventors: Ryosuke Usui, Hideki Mizuhara, Yasunori Inoue
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Publication number: 20110180933Abstract: A wiring layer is formed on a substrate, and a semiconductor device is mounted on the substrate. The wiring layer and the semiconductor device are sealed by a sealing resin. A conductive member is used to fill a through hole formed in the sealing resin in a predetermined position of the wiring layer and is provided so as to cover over the sealing resin. The metal foil is provided on the upper surface of the conductive member, and the metal foil and the wiring layer are electrically connected via the conductive member.Type: ApplicationFiled: May 29, 2009Publication date: July 28, 2011Inventors: Yasunori Inoue, Hideki Mizuhara, Ryosuke Usui, Kenichi Ezaki, Hironori Nagasaki, Mayumi Nakasato