Patents by Inventor Hideki Mizuhara

Hideki Mizuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050212091
    Abstract: A via hole is formed by a first step of forming an opening in a resin insulating film by laser radiation, a second step of forming an opening in said resin insulating film by dry etching and a third step of performing reverse sputtering in a plasma environment.
    Type: Application
    Filed: March 22, 2005
    Publication date: September 29, 2005
    Inventors: Ryosuke Usui, Yasunori Inoue, Hideki Mizuhara
  • Patent number: 6949470
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 27, 2005
    Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Publication number: 20050205996
    Abstract: A semiconductor apparatus includes a substrate and elements or semiconductor chips provided on the substrate. The elements are sealed by being brought into contact with a sealing compound. The surface of contact on the elements or the sealing compound is plasma treated. The semiconductor chip is adhesively attached to another semiconductor chip via an adhesive compound. The surface of the semiconductor chip in contact with the adhesive compound is plasma treated.
    Type: Application
    Filed: March 16, 2005
    Publication date: September 22, 2005
    Inventors: Ryosuke Usui, Atsuhiro Nishida, Hideki Mizuhara, Takeshi Nakamura
  • Patent number: 6917110
    Abstract: A semiconductor device capable of inhibiting a conductive plug from increase of resistance or disconnection resulting from moisture discharged from a first insulator film while reducing the capacitance between adjacent first interconnection layers is obtained. This semiconductor device comprises a plurality of first interconnection layers formed on a semiconductor substrate at a prescribed interval, a first insulator film, formed to fill up the clearance between the plurality of first interconnection layers, having an opening reaching the first interconnection layers and a conductive plug charged in the opening of the first insulator film and formed to be in contact with the first interconnection layers. An impurity is selectively introduced into a first region of the first insulator film in the vicinity of contact surfaces between the first interconnection layers and the conductive plug, thereby selectively modifying the first region of the first insulator film.
    Type: Grant
    Filed: December 5, 2002
    Date of Patent: July 12, 2005
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Naoteru Matsubara, Hideki Mizuhara, Takashi Goto
  • Publication number: 20050067682
    Abstract: Stacked interconnect layers each of which includes an interlayer dielectric film and an interconnect line made of copper, and solder resist layer formed as the top layer constitute a multilevel interconnect configuration. The first element, the second element and a circuit element are mounted on the surface of the configuration. The second element bonds to the first element by an adhesion layer. The upper surface of the first element is treated by plasma, and the second element is mounted on the surface.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 31, 2005
    Inventors: Ryosuke Usui, Hideki Mizuhara, Takeshi Nakamura
  • Publication number: 20050067686
    Abstract: An adhesive film is formed on an electrode film, and a coating film is formed thereon. Nickel, chrome, molybdenum, tungsten, aluminum or an alloy of them is used as a constituent material of the adhesive film. Gold, silver, platinum or an alloy of them is used as a constituent material of the coating film.
    Type: Application
    Filed: September 28, 2004
    Publication date: March 31, 2005
    Inventors: Ryosuke Usui, Hideki Mizuhara, Takeshi Nakamura
  • Publication number: 20040256742
    Abstract: In a semiconductor module, adhesion between an insulating base material and an insulator provided on the insulating base material, for example a sealing resin of the semiconductor element, is to be improved.
    Type: Application
    Filed: March 31, 2004
    Publication date: December 23, 2004
    Inventors: Ryosuke Usui, Hideki Mizuhara, Takeshi Nakamura
  • Patent number: 6825132
    Abstract: A semiconductor device including an insulation film superior in both planarization and water resistance is obtained. In this semiconductor device, a first insulation film including impurities is formed on a conductive layer. A film is formed between the first insulation film and the conductive layer for substantially preventing impurities from entering the conductive layer. Water resistance of the first insulation film is improved since impurities are included in the first insulation film. By using an insulation film superior in planarization as the first insulation film, a first insulation film superior in both planarization and water resistance can be obtained. The film provided between the first insulation film and the conductive layer prevents the impurities of the first insulation film from entering the conductive layer. Therefore, reduction in the reliability of the conductive layer can be prevented.
    Type: Grant
    Filed: January 11, 1999
    Date of Patent: November 30, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasunori Inoue, Hideki Mizuhara
  • Patent number: 6794283
    Abstract: A semiconductor device superior in reliability and suitable for microminiaturization is provided. An organic SOG film is formed on a silicon oxide film. Boron ions are implanted into the organic SOG film. By introducing boron ions into the organic SOG film, the organic components in the film are decomposed. Also, the moisture and hydroxyl group included in the film are reduced. After a metal interconnection is embedded in a modified SOG film by the Damascene method, a modified SOG film is formed thereon. Then, contact holes are formed. After a contact hole interconnection is embedded in the contact holes, a modified SOG film and an upper metal interconnection are formed by the Damascene method.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: September 21, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Shinichi Tanimoto, Atsuhiro Nishida, Yoshikazu Yamaoka, Yasunori Inoue
  • Publication number: 20040152241
    Abstract: A circuit device manufacturing method is provided, wherein contaminants attached to the top surfaces of conductive patterns 21 are removed using plasma to thereby improve the adhesion of conductive patterns 21 to a sealing resin 28. By selective etching of a conductive foil 10, separation grooves 11 are formed, thereby forming conductive patterns 21. A semiconductor element 22A and other circuit elements are mounted onto desired locations of conductive patterns 21 and electrically connected with conductive patterns 21. By irradiating plasma onto conductive foil 10 from above, contaminants attached to the surfaces of separation grooves 11 are removed.
    Type: Application
    Filed: December 1, 2003
    Publication date: August 5, 2004
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040152234
    Abstract: A circuit device manufacturing method is provided, wherein the adhesion of an overcoat resin, formed on a conductive wiring layer, to a sealing resin layer is improved by irradiating plasma onto the overcoat resin. A first conductive film 23A and a second conductive film 23B, which are laminated with an interlayer insulating layer 22 interposed in between, a reformed. By selectively removing the first conductive film, a first conductive wiring layer 12A is formed and the first conductive wiring layer is covered with an overcoat resin 18. Overcoat resin 18 is irradiated with plasma to roughen its top surface. A sealing resin layer 17 is formed so as to cover the top surface of the roughened overcoat resin 18 and circuit elements 13.
    Type: Application
    Filed: December 1, 2003
    Publication date: August 5, 2004
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Sakamoto
  • Publication number: 20040140551
    Abstract: The present invention provides a low-profile and light-weight semiconductor device having improved product reliability and higher frequency performance. A multi-layer interconnect line structure is disposed just under circuit devices 410a and 410b. An Interlayer insulating film 405 that composes a part of the multi-layer interconnect line structure is formed of a material having a relative dielectric constant within a range from 1.0 to 3.7, and a dielectric loss tangent within a range from 0.0001 to 0.02.
    Type: Application
    Filed: December 3, 2003
    Publication date: July 22, 2004
    Inventors: Ryosuke Usui, Hideki Mizuhara, Yusuke Igarashi, Noriaki Kojima, Noriaki Sakamoto
  • Publication number: 20040097086
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.
    Type: Application
    Filed: September 17, 2003
    Publication date: May 20, 2004
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Publication number: 20040097081
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a first conductive film 11 and a second conductive film 12 have been laminated via a third conductive film 13 is used. After forming a conductive pattern layer 11A by etching the first conductive film 11, anchor portions 15 are formed by overetching the third conductive film 13 by use of the conductive pattern layer 11A as a mask, and a sealing resin layer 22 is made to bite into the anchor portions 15 so as to strengthen bonding of the sealing resin layer 22 with the conductive pattern layer 11A.
    Type: Application
    Filed: September 17, 2003
    Publication date: May 20, 2004
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamota
  • Publication number: 20040092129
    Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.
    Type: Application
    Filed: September 16, 2003
    Publication date: May 13, 2004
    Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
  • Patent number: 6690084
    Abstract: A semiconductor device including an insulation film superior in insulation characteristic is obtained. Boron ions are introduced by ion implantation into an organic SOG film with a silicon nitride film formed on the organic SOG film. By this boron implantation, the property of the organic SOG film is modified. The moisture and hydroxyl group included in the film are greatly reduced irrespective of the amount of dose of ions. By using such a layered film of a modified SOG film and a silicon nitride film thereupon as an interlayer insulation film or a passivation film, the water resistance of a semiconductor device can be improved sufficiently.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: February 10, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideki Mizuhara, Hiroyuki Watanabe, Naoteru Matsubara
  • Patent number: 6617240
    Abstract: A method of fabricating a semiconductor device capable of attaining an excellent embedding characteristic also when an opening has a small diameter is obtained. According to this method of fabricating a semiconductor device, an interlayer dielectric film having an opening is formed. A first conductive member is formed in the opening by sputtering. In advance of formation of the first conductive member, first heat treatment is performed at a temperature capable of reducing the quantity of moisture and hydroxyl groups in the interlayer dielectric film. Thus, the interlayer dielectric film has a small quantity of moisture and hydroxyl groups when the first conductive member is embedded in the opening, whereby the embedding characteristic of the first conductive member is improved. Consequently, electric characteristics of a contact part can be improved also when the opening has a small diameter.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: September 9, 2003
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasunori Inoue, Naoteru Matsubara, Hidetaka Nishimura, Hideki Mizuhara
  • Publication number: 20030116853
    Abstract: A semiconductor device capable of inhibiting a conductive plug from increase of resistance or disconnection resulting from moisture discharged from a first insulator film while reducing the capacitance between adjacent first interconnection layers is obtained. This semiconductor device comprises a plurality of first interconnection layers formed on a semiconductor substrate at a prescribed interval, a first insulator film, formed to fill up the clearance between the plurality of first interconnection layers, having an opening reaching the first interconnection layers and a conductive plug charged in the opening of the first insulator film and formed to be in contact with the first interconnection layers. An impurity is selectively introduced into a first region of the first insulator film in the vicinity of contact surfaces between the first interconnection layers and the conductive plug, thereby selectively modifying the first region of the first insulator film.
    Type: Application
    Filed: December 5, 2002
    Publication date: June 26, 2003
    Inventors: Naoteru Matsubara, Hideki Mizuhara, Takashi Goto
  • Patent number: 6399478
    Abstract: A semiconductor device having a dual damascene structure having a highly reliable multilayered interconnection is applied to the present invention. A protective film (12) is formed on a first interconnection (11), and a modified SOG film (13a) is then provided thereon. An etch stopper film (14) is formed on the modified SOG film (13a), and a modified SOG film (15a) is then formed. The modified SOG film (15a), the etch stopper film (14), and the modified SOG film (13a) are etched away using a resist pattern, to form a via hole (17). The modified SOG film (15a) is etched away using the resist pattern, to form a recess (19) serving as a trench interconnection portion. The etch stopper film (14) and the protective film (12) which are exposed are removed, and the recess is filled with a conductive material (20), to form a conductive plug in the via hole and a second interconnection.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: June 4, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Naoteru Matsubara, Hideki Mizuhara
  • Patent number: 6380064
    Abstract: A semiconductor device having a semiconductor substrate and a wiring layer, which is doped with an impurity, located on the substrate. The semiconductor device has upper and lower wiring layers apart from each other. An electric insulating film electrically insulates between the upper and lower wiring layers. The insulating film has a contact hole. A wiring material is packed with the contact hole to electrically connect the upper and lower wiring layers. The impurity is contained in the lower wiring layer to decrease its resistivity.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: April 30, 2002
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideki Mizuhara, Shinichi Tanimoto, Hiroyuki Watanabe, Yasunori Inoue