Patents by Inventor Hideki Mizuhara

Hideki Mizuhara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010055873
    Abstract: A semiconductor device superior in reliability and suitable for microminiaturization is provided. An organic SOG film is formed on a silicon oxide film. Boron ions are implanted into the organic SOG film. By introducing boron ions into the organic SOG film, the organic components in the film are decomposed. Also, the moisture and hydroxyl group included in the film are reduced. After a metal interconnection is embedded in a modified SOG film by the Damascene method, a modified SOG film is formed thereon. Then, contact holes are formed. After a contact hole interconnection is embedded in the contact holes, a modified SOG film and an upper metal interconnection are formed by the Damascene method.
    Type: Application
    Filed: May 27, 1999
    Publication date: December 27, 2001
    Inventors: HIROYUKI WATANABE, HIDEKI MIZUHARA, SHINICHI TANIMOTO, ATSUHIRO NISHIDA, YOSHIKAZU YAMAOKA, YASUNORI INOUE
  • Publication number: 20010048147
    Abstract: A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first insulating film is formed from silicon oxide film materials containing greater than one percent carbon.
    Type: Application
    Filed: March 9, 1998
    Publication date: December 6, 2001
    Inventors: HIDEKI MIZUHARA, YASUNORI INOUE, HIROYUKI WATANABE, MASAKI HIRASE, KAORI MISAWA, HIROYUKI AOE, KIMIHIDE SAITO, HIROYASU ISHIHARA
  • Patent number: 6326318
    Abstract: A semiconductor device and a process for producing the same. The device has two conducting layers that are spaced from each other and an organic insulating film for electrically insulating these two conducting layers from each other. The organic insulating film contains contact holes with plugs being embedded therein so as to electrically connect these two conducting layers by the plugs. The process contains a step of forming the organic insulating film on the lower conducting layer. An impurity having a kinetic energy is introduced into the organic insulating film. Next, contact holes are formed in the organic insulating film, and then plugs are formed in the contact holes. An upper conducting layer is formed on the organic insulating film so as to be electrically connected to the plugs.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: December 4, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Kaori Misawa, Masaki Hirase, Hiroyuki Aoe
  • Publication number: 20010027009
    Abstract: A semiconductor device having a dual damascene structure having a highly reliable multilayered interconnection is applied to the present invention. A protective film (12) is formed on a first interconnection (11), and a modified SOG film (13a) is then provided thereon. An etch stopper film (14) is formed on the modified SOG film (13a), and a modified SOG film (15a) is then formed. The modified SOG film (15a), the etch stopper film (14), and the modified SOG film (13a) are etched away using a resist pattern, to form a via hole (17). The modified SOG film (15a) is etched away using the resist pattern, to form a recess (19) serving as a trench interconnection portion. The etch stopper film (14) and the protective film (12) which are exposed are removed, and the recess is filled with a conductive material (20), to form a conductive plug in the via hole and a second interconnection.
    Type: Application
    Filed: February 21, 2001
    Publication date: October 4, 2001
    Inventors: Naoteru Matsubara, Hideki Mizuhara
  • Patent number: 6288438
    Abstract: A semiconductor device that allows improvement in adhesion between insulation films having a 2-layered structure together with improvement of planarization and film characteristics, and a fabrication method thereof are obtained. In the fabrication method of the semiconductor device, an insulation film of a 2-layered structure having at least an upper layer and a lower layer is formed on a semiconductor substrate. Then, impurities are introduced into the upper insulation film under a condition where impurities arrive at least at the interface between the upper insulation film and the lower insulation film. By improving the adhesion between the upper and lower insulation films, the upper insulation film does not easily peel off.
    Type: Grant
    Filed: September 4, 1997
    Date of Patent: September 11, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideki Mizuhara, Hiroyuki Watanabe, Noriaki Kojima
  • Patent number: 6268657
    Abstract: A semiconductor device and a process for producing the same. The device has two conducting layers that are spaced from each other and an insulating film for electrically insulating these two conducting layers from each other. The insulating film contains contact holes with plugs being embedded therein so as to electrically connect these two conducting layers by the plugs. The process contains a step of forming the insulating film on the lower conducting layer. An impurity having a kinetic energy is introduced into the insulating film. Next, contact holes are formed in the insulating film, and then plugs are formed in the contact holes. An upper conducting layer is formed on the insulating film so as to be electrically connected to the plugs.
    Type: Grant
    Filed: June 18, 1997
    Date of Patent: July 31, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Kaori Misawa, Masaki Hirase, Hiroyuki Aoe
  • Publication number: 20010005628
    Abstract: A method of fabricating a semiconductor device capable of attaining an excellent embedding characteristic also when an opening has a small diameter is obtained. According to this method of fabricating a semiconductor device, an interlayer dielectric film having an opening is formed. A first conductive member is formed in the opening by sputtering. In advance of formation of the first conductive member, first heat treatment is performed at a temperature capable of reducing the quantity of moisture and hydroxyl groups in the interlayer dielectric film. Thus, the interlayer dielectric film has a small quantity of moisture and hydroxyl groups when the first conductive member is embedded in the opening, whereby the embedding characteristic of the first conductive member is improved. Consequently, electric characteristics of a contact part can be improved also when the opening has a small diameter.
    Type: Application
    Filed: December 27, 2000
    Publication date: June 28, 2001
    Applicant: Sanyo Electric Co., Ltd.
    Inventors: Yasunori Inoue, Naoteru Matsubara, Hidetaka Nishimura, Hideki Mizuhara
  • Patent number: 6235648
    Abstract: A semiconductor device including an insulation film superior in insulation characteristic is obtained. Boron ions are introduced by ion implantation into an organic SOG film with a silicon nitride film formed on the organic SOG film. By this boron implantation, the property of the organic SOG film is modified. The moisture and hydroxyl group included in the film are greatly reduced irrespective of the amount of dose of ions. By using such a layered film of a modified SOG film and a silicon nitride film thereupon as an interlayer insulation film or a passivation film, the water resistance of a semiconductor device can be improved sufficiently.
    Type: Grant
    Filed: September 25, 1998
    Date of Patent: May 22, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hideki Mizuhara, Hiroyuki Watanabe, Naoteru Matsubara
  • Patent number: 6214749
    Abstract: A semiconductor producing method includes the steps of: forming an SOG pre-film on a semimanufactured semiconductor device by means of spin-on-glass (SOG) process; and forming a modified SOG film by doping the SOG pre-film with at least one impurity ion selected from: inert gas ions; simple ions of Groups IIIb, IVb, Vb, VIb, VIIb, IVa and Va elements; and ions of compounds containing any one of Groups IIIb, IVb, Vb, VIb, VIIb, IVa and Va elements.
    Type: Grant
    Filed: October 21, 1997
    Date of Patent: April 10, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Kaori Misawa, Masaki Hirase, Hiroyuki Aoe
  • Patent number: 6177343
    Abstract: A semiconductor device and a process for producing the same. The device has two conducting layers that are spaced from each other and an insulating film for electrically insulating these two conducting layers from each other. The insulating film contains contact holes with plugs being embedded therein so as to electrically connect these two conducting layers by the plugs. The process contains a step of forming the insulating film on the lower conducting layer. An impurity having a kinetic energy is introduced into the insulating film. Next, contact holes are formed in the insulating film, and then plugs are formed in the contact holes. An upper conducting layer is formed on the insulating film so as to be electrically connected to the plugs.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: January 23, 2001
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Kaori Misawa, Masaki Hirase, Hiroyuki Aoe
  • Patent number: 6150725
    Abstract: An enclosure is formed on a substrate of a semiconductor device surrounding a bonding pad, such that a groove is formed between the enclosure and the bonding pad. An insulating film is formed over the substrate, including the enclosure and the groove. The groove and the film prevent moisture and contaminants from seeping into the semiconductor device.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: November 21, 2000
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Kaori Misawa, Hiroyasu Ishihara, Hideki Mizuhara
  • Patent number: 6071807
    Abstract: A semiconductor device including an interlayer insulation film is obtained, superior in planarization, insulation characteristics, and adhesion, suitable for microminiaturization of an element, and without inducing the problem of signal delay. In the fabrication method of this semiconductor device, an interconnection is formed on semiconductor substrate. Then, a first insulation film is formed so as to be in contact on the interconnection. Impurities are introduced into the first insulation film under a condition where the impurities arrive at least at the interconnection. As a result, the first insulation film is reduced in moisture and becomes less hygroscopic. Therefore, the insulation characteristics of the first insulation film is improved. When an SOG film superior in planarization is employed as the first insulation film, it is possible to directly form that SOG film on an underlying interconnection.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: June 6, 2000
    Assignee: Sanyo Electric Company, Ltd.
    Inventors: Hiroyuki Watanabe, Hideki Mizuhara, Kimihide Saito
  • Patent number: 5898221
    Abstract: A semiconductor device having a semiconductor substrate and a wiring layer, which is doped with an impurity, located on the substrate. The semiconductor device has upper and lower wiring layers apart from each other. An electric insulating film electrically insulates between the upper and lower wiring layers. The insulating film has a contact hole. A wiring material is packed with the contact hole to electrically connect the upper and lower wiring layers. The impurity is contained in the lower wiring layer to decrease its resistivity.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: April 27, 1999
    Assignee: Sanyo Electric Company, Ltd.
    Inventors: Hideki Mizuhara, Shinichi Tanimoto, Hiroyuki Watanabe, Yasunori Inoue
  • Patent number: 5892269
    Abstract: A semiconductor device including an insulation film superior in both planarization and water resistance is obtained. In this semiconductor device, a first insulation film including impurities is formed on a conductive layer. A film is formed between the first insulation film and the conductive layer for substantially preventing impurities from entering the conductive layer. Water resistance of the first insulation film is improved since impurities are included in the first insulation film. By using an insulation film superior in planarization as the first insulation film, a first insulation film superior in both planarization and water resistance can be obtained. The film provided between the first insulation film and the conductive layer prevents the impurities of the first insulation film from entering the conductive layer. Therefore, reduction in the reliability of the conductive layer can be prevented.
    Type: Grant
    Filed: February 26, 1997
    Date of Patent: April 6, 1999
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Yasunori Inoue, Hideki Mizuhara