Abstract: A semiconductor module comprises a first semiconductor device, a second semiconductor device and a reference voltage supplying circuit. The first semiconductor device comprises a first electrode. The second semiconductor device comprises a second electrode. The reference voltage supplying circuit is for supplying a reference potential to the first electrode and the second electrode and for suppressing a noise to be transferred between the first electrode and the second electrode.

Abstract: A motherboard for backplane buses is provided that reduces noise due to entry of external signals into signal wiring which interconnects modules, or noise due to any external signals entering a power supply after being routed around the power supply. An EBG pattern formed up of two wiring regions different from each other in impedance is periodically disposed in at least three arrays as part of the power supply layer(s) constituting a microstripline structure (one layer adjacent to a signal layer is a power supply layer, and the other layer-is interposed in air) or a stripline structure (both layers adjacent to a signal layer are power supply layers); the part of the power supply layer(s) not being involved in signal transmission between the modules on the motherboard for backplane buses.

Abstract: A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (120). The interface chip (120) has a chip select signal generation circuit that can individually activate a plurality of memory chips (110) to (113) on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).

Abstract: There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.

Abstract: In a memory module, a plurality of memories are mounted on a module base plate, impedance between Vref and Vss near each memory is coupled to Vss by a decoupling capacitor and a Vref plane to achieve low impedance configuration in a wide frequency range, Vref planes are individually provided for the respective memories, and the Vref planes are connected to each other by using a high impedance wire, or a high impedance chip part. Accordingly, a wiring technique for a module which allows effective reduction of self noise and propagation noise can be provided.

Abstract: An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.

Abstract: The present invention provides a technique which, without causing two problems, i.e., (1) increased number of power supply/grounding pins and (2) increased power feed line inductance, prevents the noise causing a problem in a control circuit, from becoming routed around and induced into an output buffer. More specifically, the above can be realized by using either of two methods: (A) providing an on-chip bypass capacitor for the control circuit and isolating a power feed route of the control circuit from that of the output buffer in an AC-like manner, or (B) designing electrical parameters (inserting resistors) such that the oscillation mode of any electrical parameter noise induced into the power feed routes will change to overdamping.

Abstract: A printed circuit board with reduced noise effects and without the need to increase the distance between a noise source and a wireless communication board. The circuit board includes multilayer structural conductive layers having a first conductive plane connected to power supply potential and a second conductive plane connected to ground potential. The first and second conductive planes are formed such that an electric field generated by a potential difference between the first conductive plane and the second conductive plane is concentrated on one side of one of the first conductive plane and the second conductive plane. The conductive plane associated with the concentrated electric field and the wireless communication board are on different sides relative to the conductive plane that is not associated with the concentrated electric field.

Abstract: A memory module bus system using a plurality of directional couplers to permit high-density packaging. A wiring line (main line) extending from a main controller and cooperating with a sub coupling line to form a directional coupler is open-ended or short-circuited to ensure that a forward wave and a reflection wave can be used to generate signals in opposite directions of the directional coupler. Memory modules are connected to opposite ends of the sub coupling line. The line length of the coupler can be half the pitch between the memory modules.

Abstract: A bus system for carrying out data transfer between one bus master and a plurality of bus slaves. The bus system includes plural directional couplers which are formed by arranging respective parts of lines drawn from the bus slaves, without being in contact with, in the neighborhood of, and in parallel with a line drawn from the bus master. The line drawn from the bus master to a terminating resistance is wired to be folded. The directional couplers are further formed by arranging parts of the lines drawn from the bus slaves alternatively with respect to a first line part of the line drawn from the bus master ranging from the bus master to a fold of the line drawn from the bus master and with respect to a second line part of the line drawn from the bus master ranging from the fold to the terminating resistance.

Abstract: In ultrahigh speed data transfer, a drive pulse is attenuated due to a skin effect and a dielectric loss, and a tail generated by a sub coupler extends as the drive pulse propagates on the main line. For that reason, an intersymbol interference becomes large, which causes jitters. In a memory system to which a plurality of DRAM memory modules are connected, in order to transfer data at high-speed, directional couplers are wired between a main controller and each of the modules, and the coupling lengths become longer with farther ends, thereby suppressing jitters. The directional couplers are wired between the main controller and each of the modules, and the coupling lengths are made longer with the farther ends with the results that the generated signal amounts are made constant, and jitters of the wiring and receiver delay are suppressed.

Abstract: There is the problem that since C/A signals in a DIMM are distributed to respective DRAMs through a register in the DIMM and DQ signals are wired directly from terminals in the DIMM, their timing is difficult to synchronize. The register for speeding up the C/A signals of the DIMM that operates with high speed is provided, and a wiring from the register is set to a daisy-chain wiring. Then, by a timing adjustment circuit provided in the DRAM, a wiring delay time difference between the C/A signals and the clock signals, which are different depending on positions of the DRAMs, is such that the sum of a delay time from the register to each DRAM and a delay amount due to the timing adjustment circuit is made equal to a delay time of the farthest DRAM.

Abstract: A printed board inspecting apparatus includes: an input unit for inputting a pulse from a first signal line; a receiving unit for receiving a voltage induced in a second signal line in response to the input pulse inputted; and a judging unit for judging whether or not a ratio between a voltage of the input pulse and the voltage induced in the second signal line is within a predetermined range. A check is made using a TDR method to determine whether or not the degree of coupling is within a range of specified values and a check is made to determine each of the voltage of the polarized RZ signal and the pulse width time is within a range of specified values to thereby inspect a printed board and a semiconductor chip constituting a bus using a directional coupler.

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: A printed circuit board in which effect of noise is reduced without increasing distance between a noise source and a wireless communication board. The above-mentioned printed circuit board is applied to an information processing apparatus having a wireless communication function. As a result, a small-sized information processing apparatus having improved throughput of wireless communication and increased communication distance is provided.

Abstract: The number of steps for preparing a layout diagram of a circuit including a coupler, which is formed by arranging a main line and a stub line in parallel with each other, is reduced. A circuit diagram editor 1902 arranges a coupler symbol 100 stored in a component symbol storage section 1904 when the coupler is arranged in preparing a circuit diagram. A layout section 1935 of a layout diagram editor 1922 layouts two wirings constituting the coupler by use of circuit diagram information and coupler information in which a coupler length and a coupler interval are defined. An object extraction section 1937 of a wiring check section 1936 extracts components and wirings from the layout diagram, and passes these to a wiring checker 1938. At this time, the coupler is passed to the wiring checker as one component that cannot be decomposed no more. Therefore, an interval between two wirings constituting the coupler is not checked.

Abstract: A fast transfer bus system capable of fast data transfer with no reflection at branch points. Four LSIs having constant-impedance interfaces are connected via two variable resistors each having three signal terminals. A variable impedance LSI is connected between these variable resistors. When the LSIs connected to the variable resistor do not work as a bus driver, three variable resistance elements in each variable resistor are set to have a value of ⅓ of the characteristic impedance Zo of connection lines, and are connected in a Y-letter shape. When one of LSIs connected to the variable resistor works as a bus driver, the values of the variable resistance elements are set to low impedance or Zo.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: A clock is located at a position close to a plurality of memory modules connected to a memory controller and located away from the controller, and wiring is carried out so that read access is preferential for transmission of read data. With respect to write data, a delay amount corresponding to a round-trip propagation delay time to each of the modules is measured and writing of the write data is carried out while maintaining a known time relationship between the clock and data. To measure round-trip reflection, lines are wired between the modules and a location detection circuit in a 1:1 relationship, and the circuit measures a time taken from a signal output time of a driver having the same impedance as that of the wired lines to a reflected-wave reception time of a hysteresis receiver.