Abstract: A data transfer method is executed to transit a three-state transmitting circuit from a high-impedance state into a data output state, transmit a preamble (dummy data) onto a bus, and sequentially transmit the essential data. The shortening of a waveform caused in the first data piece after the transition from the high-impedance state into the data output state is executed against the preamble and no shortening of a waveform is not brought about in the essential data subsequent to the preamble. This makes it possible to exclude the limitation on speeding up the data transfer imposed by the shortening of the waveform.

Abstract: There is provided a gap coupling type bus system, which makes it possible to mutually transfer data between all the modules connected to the bus. The gap coupling type bus system comprises for at least three modules, each module being provided with at least one sending/receiving circuit for sending and receiving a signal: at least three signal lines (21-26) respectively connected to the at least three modules (11-16); and terminating resistors (31-36) connected to respective signal lines at the other ends of the signal lines, each terminating resistor having generally same value as characteristic impedance of the signal line. Those at least three signal lines (21-26) have portions (1-2, 1-3, 2-3, . . . ) laid in parallel with one another with a predetermined gap, correspondingly to every combination of different two modules out of those at least three modules (11-16).

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: In a circuit simulation system, a simulator and part of device models and circuit models are stored in a server on the Internet, a user sends arbitrary circuit data to the server, the server carries out calculation using the circuit data received from the user and the device and circuit models stored therein, and then the server returns the results of calculation to the user.

Abstract: The number of steps for preparing a layout diagram of a circuit including a coupler, which is formed by arranging a main line and a stub line in parallel with each other, is reduced. A circuit diagram editor 1902 arranges a coupler symbol 100 stored in a component symbol storage section 1904 when the coupler is arranged in preparing a circuit diagram. A layout section 1935 of a layout diagram editor 1922 layouts two wirings constituting the coupler by use of circuit diagram information and coupler information in which a coupler length and a coupler interval are defined. An object extraction section 1937 of a wiring check section 1936 extracts components and wirings from the layout diagram, and passes these to a wiring checker 1938. At this time, the coupler is passed to the wiring checker as one component that cannot be decomposed no more. Therefore, an interval between two wirings constituting the coupler is not checked.

Abstract: A printed board inspecting apparatus includes: an input unit for inputting a pulse from a first signal line; a receiving unit for receiving a voltage induced in a second signal line in response to the input pulse inputted; and a judging unit for judging whether or not a ratio between a voltage of the input pulse and the voltage induced in the second signal line is within a predetermined range. A check is made using a TDR method to determine whether or not the degree of coupling is within a range of specified values and a check is made to determine each of the voltage of the polarized RZ signal and the pulse width time is within a range of specified values to thereby inspect a printed board and a semiconductor chip constituting a bus using a directional coupler.

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: In a printed board mounting method using a directional coupling bus for a high-speed data transfer, multi-bit data are transferred between nodes at a low cost. For this purpose, to transfer multi-bit data by directional coupling, a one-bit multi-coupling wiring network is vertically configured in a multilayered printed board. This minimizes the width of an area occupied by each bit along a wiring direction of the board to thereby implement a multi-bit configuration.

Abstract: A bus system with an improved propagation velocity, comprising main lines, and a plurality of stub lines provided on a one-to-one correspondence with a plurality of modules, and connecting the corresponding modules to the main lines.

Abstract: Conventionally, wiring length occupied by a directional coupler decides intervals between modules connected to a bus, and those intervals can not be shortened furthermore. Accordingly, the intervals between modules are wide and high-density mounting is not possible. In the present invention, a directional coupler in a memory bus is formed by a leader line from a controller and a leader line from a memory chip and contained within a memory module. Accordingly, pitch between the modules can be reduced and high-density mounting can be realized.

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: A memory module bus system using a plurality of directional couplers to permit high-density packaging. A wiring line (main line) extending from a main controller and cooperating with a sub coupling line to form a directional coupler is open-ended or short-circuited to ensure that a forward wave and a reflection wave can be used to generate signals in opposite directions of the directional coupler. Memory modules are connected to opposite ends of the sub coupling line. The line length of the coupler can be half the pitch between the memory modules.

Abstract: A bus system with an improved propagation velocity, comprising main lines, and a plurality of stub lines provided on a one-to-one correspondence with a plurality of modules, and connecting the corresponding modules to the main lines.

Abstract: There are provided plural synchronous RAMs, a memory controller, a bus for inputting the signal output from the memory controller 1a to the synchronous RAMs, and a bus for inputting the signals output from the synchronous RAMs to the memory controller. Each of the buses has a main line and two stub lines connected to the trunk like. Each of the synchronous RAMs is connected to the corresponding stub line so that the sum of the bus length of the bus between the synchronous RAM and the memory controller and the bus length of the bus between the synchronous RAM and the memory controller is substantially constant among all of said synchronous RAMs. Therefore, the signal transmission time between the bus master and the plural bus slaves can be shortened without increasing the number of pins of the bus master while keeping the signal transmission time substantially constant among the plural bus slaves.

Abstract: A plurality of processor elements (31 to 34) are disposed on a main board (710) in line in parallel with a first edge of the main substrate (710). Expansion board slots (331 to 336) into which an expansion board for mounting an I/O interface thereon is plugged and a memory connector (341) to which a memory board for mounting a memory thereon is connected are disposed in a region of the main substrate opposite to the first edge. The long sides of the expansion board slots (331 to 336) and the memory board connector (341) are in parallel with the first edge. A bridge LSI for executing protocol conversion between processor buses (210, 211, 212) and an I/O bus (230) and memory controllers (151, 152) for controlling memory access are disposed in regions adjacent to both the expansion board slots and the processor elements.

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: A source-clock-synchronized memory system having a large data storage capacity per memory bank and a high mounting density. The invention includes a memory unit having a first memory riser board B1 mounted on a base board through a first connector C1 and a second memory riser board B2 mounted on the base board BB through a second connector C2. The first memory riser board has a plurality of first memory modules mounted on the front surface thereof and the second memory riser board has a plurality of second memory modules mounted on the front surface thereof. The first and second memory riser boards are arranged in such a way that the back surface of the first memory riser board faces the back surface of the second memory riser board. The invention further includes a board linking connector for connecting signal lines on the first memory riser board to corresponding signal lines on the second memory riser board.

Abstract: In an information processing apparatus including a backboard having a bus for transmitting signals therethrough, at least one module, and a connector to connect the bus to the module, the backboard includes two terminators disposed respectively at both ends of the bus for providing matched termination according to a characteristic impedance of the bus to which the module is connected and a matching resistor disposed between the bus and the module. The matching resistor has a resistance value Rm represented asRm=Z1.multidot.k-Z0/2(0.8<k<1.3)where, Z1 indicates a characteristic impedance of the module, Z0 denotes the characteristic impedance of the bus, and k stands for a coefficient.