Abstract: In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film.

Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.

Abstract: A semiconductor device and manufacturing method thereof in which upon patterning of an Al strain metal wiring, an occurrence of side etch due to an emission of oxygen from an interlayer insulating film of an underlayer is prevented. A silicon nitride film or the like containing no oxygen is formed on the surface portion of an under BPSG film. A TiW film or the like serving as a barrier metal and an Al strain metal film are formed on the silicon nitride film. A side wall protecting film by carbon generated from an organic substance photoresist is preferably formed, thereby preventing the side etch of the Al strain metal film.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: A plasma processing method includes supplying a low-frequency bias to a first electrode carrying a substrate, and supplying a high-frequency power to a second electrode facing the first electrode, wherein the low-frequency bias is supplied to the first electrode in advance of staring plasma by the energy of the high-frequency power, with an electric power sufficient to form an ion-sheath on a surface of the substrate. A plasma processing apparatus is also provided.

Abstract: An autohandler for transporting a carrier which accommodates a plurality of electronic parts therein, to a test section to test electrical characteristics of the electronic parts. The autohandler comprises: a preheating section for heating or cooling the electronic parts to be tested, to a predetermined temperature; a test section for measuring electrical characteristics of the electronic parts which are heated or cooled, by electrically connecting each of the electronic parts to a testing device; a dry chamber for returning the temperature of tested electronic parts back to a normal temperature to prevent from generation of frost caused by a low temperature in the test section, and a part detecting section provided between the test section and dry chamber, for detecting whether each electronic part tested in the test section exists on a predetermined position for each electronic part to be accommodated, of the carrier.

Abstract: In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film.

Abstract: Inconvenience that an auto-handler is not normally operated which is caused when an operator forgets the fixation between a test head and the auto-handler is solved. Sensors detect whether a measuring box is in a given connection height or not and also in a connection completion position relative to the auto-handler or not and decision result output means outputs the result of decision, so that the fixation between the test head and the auto-handler can be confirmed.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: A method reduces circuit data to be simulated, by extracting element data that influences a result of simulation out of the circuit data, thereby shortening a simulation time while maintaining the accuracy of simulation. Also provided is a simulation method that employs the reduction method. The method includes the steps of entering one of an input vector and/or an observation point for the circuit data to be simulated, and extracting an element data corresponding to a node influenced by propagation of a varying state of the input signal, the varying state for the node having an influence for the observation point, from the circuit data according to the input vector and/or observation point. The extracted nodes and elements related thereto are used to prepare reduced circuit data that is simulated. The method reduces the scale of a circuit to simulate by extracting only essential elements that affect a result of simulation from circuit data such as a netlist that forms the circuit to be simulated.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film.

Abstract: In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film.

Abstract: In the timing analysis method, connection information is compared to circuit patterns that have been stored in a memory in advance after reading the connection information of an electrical circuit, a connection information supplement process to supplement vertically circuit connection information regarding the matched circuit pattern for the stored connection information is performed when the connection information is matched with one of the registered circuit patterns, and a timing analysis of the connection information that has been supplemented by the connection information supplement process is executed.

Abstract: A circuit is constructed on transistor level out of a net list and it is determined if the output node of a circuit for receiving a clock signal can go to a high impedance state from this circuit. If the output node can go to a high impedance state, it is designated as the starting point for a path searching operation and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. If, on the other hand, the output node cannot go to a high impedance state, the output node is designated as the clock node and an input node of the circuit not receiving a clock signal is designated as the terminating point of the path searching operation. With this arrangement, a sequential circuit can be divided into combinational circuits for certain.

Abstract: The present invention provide a system and a method for analyzing the static timing for LSIs which involves rather a small number of false paths contained in output results and also which reduces the processing time required.

Abstract: A column for low pressure-high speed liquid chromatography, including a column body being made of a transparent or translucent plastic and having a column chamber, said column body having one end opened and the other provided with an outflow opening, a pair of upstream and downstream filters for shutting a granular filler inside said column chamber, and a head portion being made of a plastic and detachably being fitted to said one open end of the column body and having an inflow through opening communicating with interior of said column body. A column device includes the column and a method for using the column device are also disclosed for low pressure-high speed liquid chromatography.

Abstract: A process comprising the steps of introducing an organic aluminum compound,including at least one of trialkylaluminum and dialkylhydriroaluminum, a copper chelate compound and a silane compound having one to three silicon atoms in the form of a gas mixture into a reactor holding a substrate heated to 250.degree. to 400.degree. C., forming an aluminum alloy thin film containing 0 to 5% copper and 0.1 to 2% silicon on the aforementioned substrate, and heat-treating the substrate formed with the aluminum thin film in an inert gas or hydrogen atmosphere at 400.degree. to 450.degree. C. In application of the present invention to a wiring technique of the semiconductor integrated circuit, it is possible to form a metallic thin film capable of completely smoothing a contact hole having a high aspect ratio.

Abstract: A semiconductor memory device comprises: a memory cell array having memory cells (1) arranged into a matrix pattern; a plurality of word lines (WL) each for selecting the memory cells arranged in the same line of the memory cell array; a plurality of bit lines (BL, NBL) each connected in common to the memory cells arranged in the same column of the memory cell array, for transmitting and receiving data to and from one of the memory cells selected by one of the word lines; a plurality of first column decoders (FCD) each for selectively connecting one of a predetermined number of the bit lines to one of a plurality of first common data lines (FDL, FNDL); a plurality of writing transistors (2) each provided for one of a plurality of the first common data lines and each having a data input line for inputting data applied from the outside thereto, the data inputted from the outside through the data input line being written in one of the selected memory cells so that data of a plurality of bits can be simultaneousl

Abstract: A method of making a memory cell having a transistor and a capacitor of a semiconductor memory device comprises the steps of: forming on a substrate on a surface of which the transistor is formed, an interlayer insulating film having a contact hole reaching a selected portion of the transistors; introducing a selected metal into a surface of the selected portion of the transistor exposed to the contact hole and a surface of the interlayer insulating film at portions thereof where a lower electrode of the capacitor is to be formed; forming a first conductive film having a pattern of the lower electrode of the capacitor by depositing a selected conductive material on the portions where the selected metal has been introduced; forming a capacitor insulating film on the first conductive film; and forming a second conductive film which provides an upper electrode of the capacitor on the capacitor insulating film; wherein the selected conductive material and the selected metal have such a relationship with each othe