Patents by Inventor Hideki Takeuchi

Hideki Takeuchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170301757
    Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventors: ROBERT J. MEARS, TSU-JAE KING LIU, HIDEKI TAKEUCHI
  • Patent number: 9737539
    Abstract: The present invention provides 3-[2-fluoro-5-(2,3-difluoro-6-methoxybenzyloxy)-4-methoxyphenyl]-2,4-dioxo-1,2,3,4-tetrahydrothieno[3,4-d]pyrimidine-5-carboxylic acid choline salt having excellent solubility and storage stability.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: August 22, 2017
    Assignee: KISSEI PHARMACEUTICALS CO., LTD.
    Inventors: Kazumichi Jo, Hideki Takeuchi
  • Patent number: 9722046
    Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: August 1, 2017
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert J. Mears, Tsu-Jae King Liu, Hideki Takeuchi
  • Publication number: 20170158867
    Abstract: A composition of an optical film contains silica-based hollow microparticles, a matrix precursor, a nonvolatile liquid, and a volatile solvent. The nonvolatile liquid has a vapor pressure of 500 Pa or less, a boiling point of 250° C. or higher, and a refractive index in a range from 1.4 to 1.5, inclusive. The volatile solvent is more volatile than the nonvolatile liquid. The content of the nonvolatile liquid is in the range from 5 to 30 parts by mass, inclusive, per 100 parts by mass of the sum of the silica-based hollow microparticles and the matrix precursor.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Inventors: Kenya HORI, Hirohumi INOUE, Nobuhiko SHIBATA, Hideki TAKEUCHI, Seishi SUGIMOTO
  • Publication number: 20160336407
    Abstract: A semiconductor device may include a semiconductor substrate, and a plurality of field effect transistors (FETs) on the semiconductor substrate. Each FET may include a gate, spaced apart source and drain regions on opposite sides of the gate, upper and lower vertically stacked superlattice layers and a bulk semiconductor layer therebetween between the source and drain regions, and a halo implant having a peak concentration vertically confined in the bulk semiconductor layer between the upper and lower superlattices.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 17, 2016
    Inventors: Robert J. Mears, Hideki Takeuchi
  • Publication number: 20160336406
    Abstract: A semiconductor device may include a semiconductor substrate and first transistors having a first operating voltage. Each first transistor may include a first channel and a first punch-through stop (PTS) layer in the semiconductor substrate, and the first PTS layer may be at a first depth below the first channel. The semiconductor device may further include second transistors having a second operating voltage higher than the first operating voltage. Each second transistor may include a second channel and a second PTS layer in the semiconductor substrate, and the second PTS layer may be at a second depth below the second channel that is greater than the first depth. Furthermore, the first channel may include a first superlattice, and the second channel may include a second superlattice.
    Type: Application
    Filed: May 13, 2016
    Publication date: November 17, 2016
    Inventors: Robert J. Mears, Hideki Takeuchi
  • Patent number: 9406753
    Abstract: A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: August 2, 2016
    Assignee: ATOMERA INCORPORATED
    Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
  • Publication number: 20160149023
    Abstract: A semiconductor device may include a substrate having a channel recess therein, a plurality of spaced apart shallow trench isolation (STI) regions in the substrate, and source and drain regions spaced apart in the substrate and between a pair of the STI regions. A superlattice channel may be in the channel recess of the substrate and extend between the source and drain regions, with the superlattice channel including a plurality of stacked group of layers, and each group of layers of the superlattice channel including stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A replacement gate may be over the superlattice channel.
    Type: Application
    Filed: November 23, 2015
    Publication date: May 26, 2016
    Inventors: Robert J. Mears, Tsu-Jae King LIU, Hideki Takeuchi
  • Publication number: 20160120511
    Abstract: A modulation frequency control unit (36) controls a displacement-use transmission unit (34) such that displacement-use ultrasonic beam (EB) is subjected to modulation processing using a relatively high modulation frequency and a relatively low modulation frequency. A displacement measurement unit (24) measures the displacement of a tissue in a treatment area (P) at each of the modulation frequencies, and a coagulation measurement unit (25) measures local coagulation in the treatment area (P) on the basis of the measurement result of the displacement at the relatively high modulation frequency, and measures wide-area coagulation in the treatment area (P) on the basis of the measurement result of the displacement at the relatively low modulation frequency.
    Type: Application
    Filed: May 27, 2014
    Publication date: May 5, 2016
    Applicants: THE UNIVERSITY OF TOKYO, HITACHI ALOKA MEDICAL, LTD.
    Inventors: Takashi Azuma, Akira Sasaki, Ryosuke Aoyagi, Shu Takagi, Kazunori Itani, Keisuke Fujiwara, Hideki Takeuchi
  • Publication number: 20160099317
    Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
    Type: Application
    Filed: December 3, 2015
    Publication date: April 7, 2016
    Inventors: ROBERT MEARS, HIDEKI TAKEUCHI, ERWIN TRAUTMANN
  • Publication number: 20160082010
    Abstract: An objective of the present invention is to improve the solubility of 3-[2-fluoro-5-(2,3-difluoro-6-methoxybenzyloxy)-4-methoxyphenyl]-2,4-dioxo-1,2,3,4-tetrahydrothieno[3,4-d]pyrimidine-5-carboxylic acid. The present invention provides 3-[2-fluoro-5-(2,3-difluoro-6-methoxybenzyl-oxy)-4-methoxyphenyl]-2,4-dioxo-1,2,3,4-tetrahydrothieno[3,4-d]pyrimidine-5-carboxylic acid choline salt has excellent solubility and storage stability.
    Type: Application
    Filed: September 28, 2015
    Publication date: March 24, 2016
    Applicant: KISSEI PHARMACEUTICAL CO., LTD.
    Inventors: Kazumichi JO, Hideki TAKEUCHI
  • Patent number: 9275996
    Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
    Type: Grant
    Filed: November 21, 2014
    Date of Patent: March 1, 2016
    Assignee: MEARS TECHNOLOGIES, INC.
    Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
  • Patent number: 9205872
    Abstract: A vehicle body structure is provided to avoid the damage to a battery pack due to invasion of an electric device in a side impact crash. The vehicle body structure includes a battery pack on its inner side in a vehicle width direction, and an electric device on its outer side. A No1 seat cross member 5 is provided along in the vehicle width direction of the floor panel 3. The No1 seat cross member 5 is provided with a weak portion 54 in a position in the vehicle width direction corresponding to between the battery pack 2 and an electric hot-water heater 9 as the electric device.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: December 8, 2015
    Assignee: MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Yusuke Okada, Hideki Takeuchi
  • Patent number: 9169266
    Abstract: An objective of the present invention is to improve the solubility of 3-[2-fluoro-5-(2,3-difluoro-6-methoxybenzyloxy)-4-methoxyphenyl]-2,4-dioxo-1,2,3,4-tetrahydrothieno[3,4-d]pyrimidine-5-carboxylic acid. The present invention provides 3-[2-fluoro-5-(2,3-difluoro-6-methoxybenzyl-oxy)-4-methoxyphenyl]-2,4-dioxo-1,2,3,4-tetrahydrothieno[3,4-d]pyrimidine-5-carboxylic acid choline salt has excellent solubility and storage stability.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: October 27, 2015
    Assignee: KISSEI PHARMACEUTICAL CO., LTD.
    Inventors: Kazumichi Jo, Hideki Takeuchi
  • Publication number: 20150144877
    Abstract: A semiconductor device may include a substrate, and a plurality of fins spaced apart on the substrate. Each of the fins may include a lower semiconductor fin portion extending vertically upward from the substrate, and at least one superlattice punch-through layer on the lower fin portion. The superlattice punch-through layer may include a plurality of stacked groups of layers, with each group of layers of the superlattice punch-through layer comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. Each fin may also include an upper semiconductor fin portion on the at least one superlattice punch-through layer and extending vertically upward therefrom. The semiconductor device may also include source and drain regions at opposing ends of the fins, and a gate overlying the fins.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
  • Publication number: 20150144878
    Abstract: A semiconductor device may include an alternating stack of superlattice and bulk semiconductor layers on a substrate, with each superlattice layer including a plurality of stacked group of layers, and each group of layers of the superlattice layer including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include spaced apart source and drain regions in an upper bulk semiconductor layer of the alternating stack of superlattice and bulk semiconductor layers, and a gate on the upper bulk semiconductor layer between the spaced apart source and drain regions.
    Type: Application
    Filed: November 21, 2014
    Publication date: May 28, 2015
    Inventors: Robert Mears, Hideki Takeuchi, Erwin Trautmann
  • Patent number: 8978804
    Abstract: A battery box includes a flange, a side wall and a bottom wall. The flange is connected to an inner peripheral edge of an installation hole formed in a floor panel of a vehicle. The side wall gently continues with the flange, and is extended downward. The bottom wall, has a periphery gently continuing with the side wall, and is formed with at least one open hole in a center of the bottom wall. Seat portions are projected upper than the bottom wall. At least one seat portion is disposed at each both sides of the open hole. A bottom cover closes the open hole. A corner portion gently continues with the side wall and the bottom wall forming curved surface. A center of curvature of the curved surface is set inside a corner of a battery to be placed on the seat portions.
    Type: Grant
    Filed: July 22, 2013
    Date of Patent: March 17, 2015
    Assignees: Mitsubishi Jidosha Kogyo Kabushiki Kaisha, Mitsubishi Jidosha Engineering Kabushiki Kaisha
    Inventors: Hideo Okada, Hideki Takeuchi
  • Publication number: 20140338997
    Abstract: A vehicle body structure is provided to avoid the damage to a battery pack due to invasion of an electric device in a side impact crash. The vehicle body structure includes a battery pack on its inner side in a vehicle width direction, and an electric device on its outer side. A No1 seat cross member 5 is provided along in the vehicle width direction of the floor panel 3. The No1 seat cross member 5 is provided with a weak portion 54 in a position in the vehicle width direction corresponding to between the battery pack 2 and an electric hot-water heater 9 as the electric device.
    Type: Application
    Filed: May 19, 2014
    Publication date: November 20, 2014
    Applicant: Mitsubishi Jidosha Kogyo Kabushiki Kaisha
    Inventors: Yusuke OKADA, Hideki TAKEUCHI
  • Patent number: 8727428
    Abstract: A front part body structure of a vehicle, includes: an upper frame which is extended in a longitudinal direction of the vehicle, one end of which is joined to a front pillar, and which includes an inner panel and an outer panel, the outer panel that is divided in a dividing part in the longitudinal direction of the vehicle; and a first partition wall which is provided between the inner panel and the outer panel, one end of which is joined to the inner panel, and the other end of which is fastened and fixed to the dividing part of the outer panel by means of a fastening member.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Jidosha Kogyo Kabushiki Kaisha
    Inventors: Hideki Takeuchi, Akihiro Matsui
  • Publication number: 20140020969
    Abstract: A battery box includes a flange, a side wall and a bottom wall. The flange is connected to an inner peripheral edge of an installation hole formed in a floor panel of a vehicle. The side wall gently continues with the flange, and is extended downward. The bottom wall, has a periphery gently continuing with the side wall, and is formed with at least one open hole in a center of the bottom wall. Seat portions are projected upper than the bottom wall. At least one seat portion is disposed at each both sides of the open hole. A bottom cover closes the open hole. A corner portion gently continues with the side wall and the bottom wall forming curved surface. A center of curvature of the curved surface is set inside a corner of a battery to be placed on the seat portions.
    Type: Application
    Filed: July 22, 2013
    Publication date: January 23, 2014
    Applicants: MITSUBISHI JIDOSHA ENGINEERING KABUSHIKI KAISHA, MITSUBISHI JIDOSHA KOGYO KABUSHIKI KAISHA
    Inventors: Hideo OKADA, Hideki TAKEUCHI