Abstract: A semiconductor memory device comprising: a first memory cell array including a plurality of memory cells, a first switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the first memory cell array, a latch circuit for latching the data transferred from the first switch circuit, a first write selector circuit for transferring the data transferred from the latch circuit, a first bit line connected to at least one of the plurality of memory cells and receiving the data transferred from the first write selector circuit, a second memory cell array including a plurality of memory cells that are different from the plurality of memory cells arranged in the first memory cell array, a second switch circuit for transferring data to be programmed to at least one of the plurality of memory cells arranged in the second memory cell array, a second write selector circuit connected to the second switch circuit and transferring the data transferred from the second sw

Abstract: In fabricating a microelectromechanical structure (MEMS), a method of forming a narrow gap in the MEMS includes a) depositing a layer of sacrificial material on the surface of a supporting substrate, b) photoresist masking and at least partially etching the sacrificial material to form at least one blade of sacrificial material, c) depositing a structural layer over the sacrificial layer, and d) removing the sacrificial layer including the blade of the sacrificial material with a narrow gap remaining in the structural layer where the blade of sacrificial material was removed.

Abstract: A semiconductor integrated circuit device comprises a semiconductor memory circuit including a memory cell array in which normal cells are integrated and a fuse circuit in which fuse cells that store operation information of the semiconductor memory circuit are integrated. The fuse cell is of a 2-transistor type memory cell which comprises a cell transistor having a charge storage layer and a selection transistor which selects the cell transistor.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: The present invention provides a novel crystalline form of n-butyl[4-[2-[2-hydroxy-5-(N-hydroxycarbamimidoyl) benzenesulfonylamino]ethyl]-2?-methanesulfonyl-3-yloxy] acetate hydrochloride, pharmaceutical compositions containing the same and their uses, which exhibits excellent inhibitory activities against activated blood coagulation factor X, and is useful for the treatment or prevention of a tromboembolic disease.

Abstract: A semiconductor memory device has access transistors with a gate and a pair of impurity diffusion layers formed on a semiconductor substrate and memory capacitors with a storage node electrode and a cell plate electrode. The electrodes are connected to each other via a capacitive insulating layer made of a ferroelectric material. The storage node electrode has a surface covered with the capacitive insulating layer and is formed in a shape of column on one of the pair of impurity diffusion layers in a hole formed from an inter-layer insulating film covering the access transistor to the one of the pair of impurity diffusion layers. A upper surface of the column does not exceed the inter-layer insulating film. The storage node electrode formed in the hole face the cell plate electrode via the inter-layer insulating film.

Abstract: A plurality of 2D sub arrays are defined on a 2D array transducer for effecting transmission and reception of ultrasound. For each sub array, a plurality of groups are set. More specifically, a plurality of (16, for example) transducer elements forming a sub array are grouped or divided into a plurality of (4, for example) groups. A multiplexer sums a plurality of receiving signals output from the plurality of transducer elements for each group, and generates a group receiving signal. A plurality of group receiving signals thus generated are then subjected to a sub phase adjusting and summing process to form a sub phase adjusted and summed signal. A plurality of sub phase adjusted and summed signals corresponding to the plurality of sub arrays are then subjected to a main phase adjusting and summing process. A sub phase adjusting and summing processing section is provided within a probe head, a cable connector, or an apparatus body.

Abstract: In an ultrasound diagnosis apparatus, a plurality of sub arrays are defined on a 2D array transducer. The sub array shape pattern of each sub array is adaptively changed in accordance with the beam scanning direction. Each sub array is composed of a plurality of groups, each of which is composed of a plurality of transducer elements. With the change of sub array shape pattern in accordance with a beam scanning direction, the group shape pattern of each group also changes. The sub array shape changes for each sub array, and a variable region is determined by the largest outer edge of the shape changed. The variable regions partially overlap with each other among a plurality of sub arrays. On a 2D array transducer, a plurality of sub arrays are always closely coupled with each other even when each sub array shape is changed.

Abstract: The present invention relates to a 5-amidino-N-(2-aminophenethyl)-2-hydroxybenzenesulfonamide derivative represented by the general formula: 1

Abstract: A method of improving wear-resistance and anti-seizing properties of slide surface of machineries, such as outer slide surfaces of piston pins of vehicle engines, wherein slide surfaces of iron or steel base materials of machineries are first processed carburizing, then the carburized surfaces are plated with chromium, and next the chromium-plated surfaces undergo impulses fine peening to produce lubricant-retaining cavities on the slide surfaces, which include fine cavities in the form of depressions in the chromium-plating layer and relatively large cavities produced by exfoliation of the chromium-plating layer.

Abstract: A clipping device able to reduce the number of processing cycles, able to simplify the circuit, and able to increase the speed of the processing, having a clip code generation circuit for generating clip codes corresponding to results of comparison of vertex coordinates of a primitive and a judgment reference value of a multi-dimensional region and a negative value of the judgment reference value for the vertexes of the primitive; a current clip register for shifting the clip codes; clip registers able to replace the clip codes in accordance with a control signal; a control circuit outputting a control signal so as to replace the clip codes between clip registers when receiving a replacement instruction; and a logic circuit for performing a logic operation with respect to all bit data set in the clip registers and setting a clip flag indicating whether or not the vertex to be judged is inside or outside a multi-dimensional region of an object to be drawn.

Abstract: A plasma processing method comprises the steps of supplying a low-frequency bias to a first electrode carrying a substrate, and supplying a high-frequency power to a second electrode facing the first electrode, wherein the low-frequency bias is supplied to the first electrode in advance of starting plasma by the energy of the high-frequency power, with an electric power sufficient to form an ion-sheath on the surface of the substrate.

Abstract: This invention relates to a method for boring a large-section tunnel safely and quickly by reinforcing and improving in advance the ground over the full length of the tunnel section, which includes; boring a top drift (2) through the full length of the tunnel (1) section, drilling curved holes inclined in forward or backward directions at an angle of about 45 degrees at preset intervals from the top drift (2) along the peripheral edges of the sections of the tunnel (1) by using ordinary small bore rock drills and curved steel pipes (3), pulling off the steel pipes (3) after inserting injection pipes into the drilled holes, injecting grout into the ground surrounding the tunnel through the injection pipes to develop artificial ground arches (4), excavating the tunnel (1), advancing suspension forms (6) and placing concrete for secondary lining.

Abstract: The present invention provides an noise suppression circuit comprises an internal circuit which has a high and a low level terminals. The low level terminal is connected to a low level power supply (GND) line. The noise suppression circuit further comprises a first transistor in which one main electrode is connected to the high level terminal of the circuit, a bypass capacitor connected between the other main electrode of the first transistor and the low level power supply line, and a second transistor connected between the other main electrode of the first transistor and a high level power supply (VDD) line. The first transistor is conductive when the internal circuit is active, and is not conductive when the internal circuit is inactive. The second transistor is not conductive when the internal circuit is active, and is conductive when the internal circuit is inactive.

Abstract: For the purpose of improving wear-resistance and anti-seizing property of slide surfaces of machineries, such as outer slide surfaces of piston pins of vehicle engines, slide surfaces of iron or steel base materials of machineries are first processed by carburizing, then the carburized surfaces are plated with chromium, and next the chromium-plated surfaces undergo impulses by shot peening to produce lubricant-retaining cavities on the slide surfaces, which include fine cavities in the form of depressions in the chromium-plating layer and relatively large cavities produced by exfoliation of the chromium-plating layer.

Abstract: The method of the present invention comprises the steps of: provisionally updating a resource through a first transaction program and locking the resource; determining if a second transaction program generates a request to update the resource which has been locked because of the provisional update through the first transaction program; making the second transaction program exclusively wait and reproducing a third transaction program having an internal status identical to that of the second transaction program when the second transaction program generates the update request; providing a virtual resource having an original status before the provisional update through the first transaction program; provisionally updating the virtual resource through the third transaction program without exclusive wait; and rolling back and closing the exclusively waiting second transaction program and executing commit in the reproduced third transaction program when rollback of the first transaction program is executed due to an

Abstract: A plasma processing method comprises the steps of supplying a low-frequency bias to a first electrode carrying a substrate, and supplying a high-frequency power to a second electrode facing the first electrode, wherein the low-frequency bias is supplied to the first electrode in advance of starting plasma by the energy of the high-frequency power, with an electric power sufficient to form an ion-sheath on the surface of the substrate.

Abstract: A design support system includes an information merging section, a connection information generating section and an inter-semiconductor chip and lead frame connection information integrating section. The information merging section captures semiconductor chip information and lead frame information, and generates semiconductor chip and lead frame merged information for each of semiconductor chips. The connection information generating section generates connection information between the semiconductor chips and lead frame from the semiconductor chip and lead frame merged information generated by the information merging section.

Abstract: In a semiconductor storage device, an access transistor, which has a gate electrode and a pair of impurity diffusion layers, is formed at a device activation region defined by a device isolation structure of a semiconductor substrate. A first insulating film, which has a first contact hole for exposing a portion of the surface of one of the pair of impurity diffusion layers, is formed over the access transistor. A protective film, which has a second contact hole formed on the first contact hole, is formed on the first insulating film. A second insulating film is formed on the side wall faces of the first and second contact holes. A memory capacitor has a lower electrode and an upper part electrode which are opposed each other and are capacitive-coupled through a dielectric film.

Abstract: A noise suppression circuit encompasses an internal circuit, a bypass capacitor, first and second transistors. The internal circuit has high and low level terminals, and the low level terminal is connected to a low level power supply line. The internal circuit is supplied with enable and inverted enable signals. The first transistor has a first control electrode, and one main electrode is connected to the high level terminal. The first control electrode is supplied with the inverted enable signal. The bypass capacitor is connected between the other main electrode of the first transistor and the low level power supply line. The second transistor is connected between the other main electrode of the first transistor and a high level power supply line. The second transistor has a second control electrode supplied with the enable signal. The second transistor is not conductive when the internal circuit is active.