Patents by Inventor Hidemi Takasu
Hidemi Takasu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10184894Abstract: A target is irradiated in a time-shared manner with a visible-light-range illumination light source and an infrared laser beam for Raman scattering, and a target image is formed with an image-capturing lens on a CIGS image sensor provided with a visible-light-range filter, a narrow-band infrared filter for Raman-scattered light measurement, and a near-band reference narrow-band infrared filter that does not let Raman-scattered light pass through. In a preliminary measurement, a plurality of normal sections are measured and averaged, and by using the same as a reference, an actual measurement of Raman scattering is performed. In displaying a visible-light image with the CIGS image sensor, superimposed display is performed to specify sections where Raman scattering is detected, and superimposed display positions are corrected in association with focusing and zooming. The displaying of the visible-light image is continued even during the detection of Raman scattering.Type: GrantFiled: August 21, 2014Date of Patent: January 22, 2019Assignee: Rohm Co., Ltd.Inventors: Hidemi Takasu, Toshihisa Maeda, Masahide Tanaka, Takuji Maekawa
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Publication number: 20160077008Abstract: A target is irradiated in a time-shared manner with a visible-light-range illumination light source and an infrared laser beam for Raman scattering, and a target image is formed with an image-capturing lens on a CIGS image sensor provided with a visible-light-range filter, a narrow-band infrared filter for Raman-scattered light measurement, and a near-band reference narrow-band infrared filter that does not let Raman-scattered light pass through. In a preliminary measurement, a plurality of normal sections are measured and averaged, and by using the same as a reference, an actual measurement of Raman scattering is performed. In displaying a visible-light image with the CIGS image sensor, superimposed display is performed to specify sections where Raman scattering is detected, and superimposed display positions are corrected in association with focusing and zooming. The displaying of the visible-light image is continued even during the detection of Raman scattering.Type: ApplicationFiled: August 21, 2014Publication date: March 17, 2016Inventors: Hidemi Takasu, Toshihisa Maeda, Masahide Tanaka, Takuji Maekawa
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Patent number: 8044434Abstract: The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer.Type: GrantFiled: August 22, 2007Date of Patent: October 25, 2011Assignee: Rohm Co., Ltd.Inventors: Hiroaki Ohta, Hidemi Takasu
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Patent number: 7999286Abstract: The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride semiconductor layer of the first conductivity type stacked thereon; a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over these first, second and third group III-V nitride semiconductor layers; a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer via the gate insulating film; a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate; a drain electrode formed in contaType: GrantFiled: August 22, 2007Date of Patent: August 16, 2011Assignee: Rohm Co., Ltd.Inventors: Hiroaki Ohta, Hidemi Takasu
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Publication number: 20100006894Abstract: The semiconductor device includes a P-type group III-V nitride semiconductor layer, an N-type group III-V nitride semiconductor layer, and an electrode in contact with both of the P-type group III-V nitride semiconductor layer and the N-type group III-V nitride semiconductor layer. The electrode includes a first electrode portion made of a first conductive material, and a second electrode portion, made of a second conductive material different from the first conductive material, bonded to the first electrode portion. The first electrode portion is in contact with the P-type group III-V nitride semiconductor layer, and the second electrode portion is in contact with the N-type group III-V nitride semiconductor layer.Type: ApplicationFiled: August 22, 2007Publication date: January 14, 2010Applicant: ROHM CO., LTD.Inventors: Hiroaki Ohta, Hidemi Takasu
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Publication number: 20090321854Abstract: An MIS field effect transistor includes a nitride semiconductor multilayer structure including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type which is arranged on the first group III-V nitride semiconductor layer, and a third group III-V nitride semiconductor layer of the first conductivity type which is arranged on the second group III-V nitride semiconductor layer. A gate insulating film is formed on a wall surface ranging over the first, second and third group III-V nitride semiconductor layers so that the film stretches over the first, second and third group III-V nitride semiconductor layer. A gate electrode made of a conductive material is formed so that it faces the second group III-V nitride semiconductor layer via the gate insulating film.Type: ApplicationFiled: August 22, 2007Publication date: December 31, 2009Inventors: Hiroaki Ohta, Hidemi Takasu, Hirotaka Otake
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Publication number: 20090278197Abstract: The MIS field-effect transistor includes: a substrate; a nitride semiconductor multilayer structure portion formed on the substrate, including a first group III-V nitride semiconductor layer of a first conductivity type, a second group III-V nitride semiconductor layer of a second conductivity type stacked thereon and a third group III-V nitride semiconductor layer of the first conductivity type stacked thereon; a gate insulating film formed on a wall surface formed over the first, second and third group III-V nitride semiconductor layers to extend over these first, second and third group III-V nitride semiconductor layers; a gate electrode made of a conductive material formed as being opposed to the second group III-V nitride semiconductor layer via the gate insulating film; a drawn portion electrically connected to the first group III-V nitride semiconductor layer and drawn from the nitride semiconductor multilayer structure portion in a direction parallel to the substrate; a drain electrode formed in contaType: ApplicationFiled: August 22, 2007Publication date: November 12, 2009Applicant: ROHM CO., LTDInventors: Hiroaki Ohta, Hidemi Takasu
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Patent number: 7605012Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.Type: GrantFiled: June 27, 2005Date of Patent: October 20, 2009Assignees: National Institute of Advanced Industrial Science & Tech., Rohm Co., Ltd.Inventors: Shigeru Niki, Paul Fons, Kakuya Iwata, Tetsuhiro Tanabe, Hidemi Takasu, Ken Nakahara
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Patent number: 7464131Abstract: A logical calculation circuit capable of storing data, and performing logical calculations with high reliability and high speeds are provided. The residual polarized state s? of a load ferroelectric capacitor Cs? is actively changed so that the residual polarized state s? of a load ferroelectric capacitor Cs? is opposite to the residual polarized state s of a storage ferroelectric capacitor Cs. In the case a reference potential is made c=0 in the calculation operation, even if the second data to be calculated x=1 is given to the storage ferroelectric capacitor Cs in the residual polarized state s (the first data to be calculated)=0, the ferroelectric capacitor Cs does not reverse in polarity. Even with combinations other than s=0 and x=1, the ferroelectric capacitor Cs does not reverse in polarity.Type: GrantFiled: February 2, 2004Date of Patent: December 9, 2008Assignee: Rohm Co., Ltd.Inventors: Michitaka Kameyama, Takahiro Hanyu, Hiromitsu Kimura, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
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Patent number: 7450412Abstract: To provide a logical operation circuit which can perform a logical operation using a ferroelectric capacitor and a logical operation method. A logical operation circuit 1 has a ferroelectric capacitors CF and a transistor MP. The ferroelectric capacitor CF can retain a polarization state P1 (y=1) or P2 (y=0) corresponding to first operation target data y. In an operation process, a first terminal 3 of the ferroelectric capacitor 1 is precharged to a source potential Vdd, and a potential corresponding to second operation target data x, that is, a ground potential GND (x=1) or the source potential Vdd (x=0), is given to a second terminal 5 of the ferroelectric capacitor via a bit line BL. When the threshold voltage Vth of the transistor MP is set properly, the transistor MP becomes on or off (on, on, on, off) depending on the combination of x and y (0-0, 0-1, 1-0, 1-1).Type: GrantFiled: January 22, 2003Date of Patent: November 11, 2008Assignee: Rohm Co., Ltd.Inventors: Michitaka Kameyama, Takahiro Hanyu, Hiromitsu Kimura, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
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Patent number: 7026841Abstract: To provide a logical operation circuit and a logical operation method which can perform a logical operation using a ferroelectric capacitor. A logical operation circuit 1 has ferroelectric capacitors CF1 and CF2 and a transistor MP. The ferroelectric capacitor CF1 can retain a polarization state P1 corresponding to a logical operator. In an operation and storage process, a source potential Vdd corresponding to first operation target data y1=1 and a ground potential GND corresponding to second operation target data y2=0 are given to a first terminal 3 and a second terminal 5, respectively, of the ferroelectric capacitor CF1. The polarization state of the ferroelectric capacitor CF1 is thereby shifted to P4. A residual polarization state corresponding to the polarization state P4 is P2. The residual polarization state changes (P1, P1, P2 or P1) depending on the combination of y1 and y2 (0-0, 0-1, 1-0 and 1-1).Type: GrantFiled: January 22, 2003Date of Patent: April 11, 2006Assignee: Rohm Co., Ltd.Inventors: Michitaka Kameyama, Takahiro Hanyu, Hiromitsu Kimura, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
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Patent number: 6987029Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.Type: GrantFiled: November 17, 2003Date of Patent: January 17, 2006Assignees: National Institute of Advanced Industrial Science and Technology, Rohm Co., Ltd.Inventors: Shigeru Niki, Paul Fons, Kakuya Iwata, Tetsuhiro Tanabe, Hidemi Takasu, Ken Nakahara
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Publication number: 20050247954Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.Type: ApplicationFiled: June 27, 2005Publication date: November 10, 2005Inventors: Shigeru Niki, Paul Fons, Kakuya Iwata, Tetsuhiro Tanabe, Hidemi Takasu, Ken Nakahara
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Publication number: 20050152198Abstract: To provide a logical operation circuit and a logical operation method which can perform a logical operation using a ferroelectric capacitor. A logical operation circuit 1 has ferroelectric capacitors CF1 and CF2 and a transistor MP. The ferroelectric capacitor CF1 can retain a polarization state P1 corresponding to a logical operator. In an operation and storage process, a source potential Vdd corresponding to first operation target data y1=1 and a ground potential GND corresponding to second operation target data y2=0 are given to a first terminal 3 and a second terminal 5, respectively, of the ferroelectric capacitor CF1. The polarization state of the ferroelectric capacitor CF1 is thereby shifted to P4. A residual polarization state corresponding to the polarization state P4 is P2. The residual polarization state changes (P1, P1, P2 or P1) depending on the combination of y1 and y2 (0-0, 0-1, 1-0 and 1-1).Type: ApplicationFiled: January 22, 2003Publication date: July 14, 2005Inventors: Michitaka Kameyama, Takahiro Hanyu, Hiromitsu Kimura, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
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Publication number: 20050146922Abstract: To provide a logical operation circuit which can perform a logical operation using a ferroelectric capacitor and a logical operation method. A logical operation circuit 1 has a ferroelectric capacitors CF and a transistor MP. The ferroelectric capacitor CF can retain a polarization state P1 (y=1) or P2 (y=0) corresponding to first operation target data y. In an operation process, a first terminal 3 of the ferroelectric capacitor 1 is precharged to a source potential Vdd, and a potential corresponding to second operation target data x, that is, a ground potential GND (x=1) or the source potential Vdd (x=0), is given to a second terminal 5 of the ferroelectric capacitor via a bit line BL. When the threshold voltage Vth of the transistor MP is set properly, the transistor MP becomes on or off (on, on, on, off) depending on the combination of x and y (0-0, 0-1, 1-0, 1-1).Type: ApplicationFiled: January 22, 2003Publication date: July 7, 2005Applicant: Rochim Co., Ltd.Inventors: Michitaka Kameyama, Takahiro Hanyu, Hiromitsu Kimura, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu
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Patent number: 6884701Abstract: A process for fabricating a semiconductor device having a buried layer comprises the steps of implanting an impurity ion into where the buried layer to be formed in a substrate, providing the substrate inside a reactor furnace, preparing a nonoxidizing atmosphere inside of the reactor furnace, annealing the substrate to activate and diffuse the implanted impurity ion region while increasing inside temperature of the reactor furnace up to a first temperature, and shifting the inside temperature of the reactor furnace from the first temperature to a second temperature in which a epitaxial crystal starts to grow and introducing a epitaxial growth gas into the reactor furnace to grow an epitaxial layer on a surface of the substrate.Type: GrantFiled: December 16, 1998Date of Patent: April 26, 2005Inventor: Hidemi Takasu
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Patent number: 6853027Abstract: A semiconductor nonvolatile memory cell comprised of a p-type silicon well 12, an n+ drain 8 and an n+ source 10, the source and the drain regions defining an channel region 7. On top of the well 12 there are laminated a thin silicon dioxide film 2 served as a gate oxide, a polysilicon layer 32 and a SrTiO3 layer 34 comprised of a high dielectric substance, in respective order. Further on top of these layers, there is formed a polysilicon layer 36 served as gate electrode. By using the memory cell and appropriate select transistors, a semiconductor nonvolatile memory device is constructed.Type: GrantFiled: October 4, 1996Date of Patent: February 8, 2005Assignee: Rohm Company, Ltd.Inventor: Hidemi Takasu
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Publication number: 20040099876Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.Type: ApplicationFiled: November 17, 2003Publication date: May 27, 2004Applicant: National Institute of Advanced Industrial Science and Technology and Rohm Co., Ltd.Inventors: Shigeru Niki, Paul Fons, Kakuya Iwata, Tetsuhiro Tanabe, Hidemi Takasu, Ken Nakahara
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Patent number: 6741489Abstract: The present invention provides a practical device which can hold data even if the power is shut OFF, and more particularly to a data holding device which has a high detection margin at data restoration and has high reliability. The data holding device 1 comprises a data latch circuit 3 and a composite capacitor 5. The data holding device 1 can store the data in the ferroelectric capacitors 17 and 19 in a non-volatile way. A voltage the same as the power supply voltage VDD is applied across the composite capacitor 5 where the ferroelectric capacitors 17 and 19 are connected in a series, and data is restored by detecting the voltage which is generated at the connection node 5a at this time. As a result, the detection margin can be dramatically increased.Type: GrantFiled: November 12, 2002Date of Patent: May 25, 2004Assignee: Rohm Co., Ltd.Inventors: Hidemi Takasu, Tsuneo Fujikawa
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Patent number: 6674098Abstract: A light emitting device includes a silicon substrate (1), a silicon nitride film (2) formed on the surface of the silicon substrate (1), at least an n-type layer (3), (4) and a p-type layer (6), (7) which are formed on the silicon nitride film (2) and also which are made of a ZnO based compound semiconductor, and a semiconductor layer lamination (11) in which layers are laminated to form a light emitting layer. Preferably this silicon nitride film (2) is formed by thermal treatment conducted in an atmosphere containing nitrogen such as an ammonium gas. Also, in another embodiment, a light emitting device is formed by growing a ZnO based compound semiconductor layer on a main face of a sapphire substrate, the main face being perpendicular to the C-face thereof. As a result, it is possible to obtain a device using a ZnO based compound with high properties such as an LED very excellent in crystallinity and having a high light emitting efficiency.Type: GrantFiled: January 25, 2002Date of Patent: January 6, 2004Assignees: National Institute of Advanced Industrial Science and Technology, Rohm Co., Ltd.Inventors: Shigeru Niki, Paul Fons, Kakuya Iwata, Tetsuhiro Tanabe, Hidemi Takasu, Ken Nakahara