Patents by Inventor Hidemitsu Aoki

Hidemitsu Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8420549
    Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer having a device area, an end face, and a surface peripheral area located outside the device area and between the end face and the device area. Forming a Cu layer on the semiconductor wafer and rotating the wafer in a horizontal plane. Emitting a first liquid from an edge nozzle towards the surface peripheral area which selectively removes a first unnecessary material in the surface peripheral area. Emitting a protecting liquid toward the semiconductor wafer, thereby protecting the device area from the first liquid. An angle of a longitudinal axis of the edge nozzle with respect to a tangent of the semiconductor wafer at a point, where the longitudinal axis of the edge nozzle intersects the end face of the wafer, is set in the range of 0 to 90 degrees in plan view.
    Type: Grant
    Filed: November 24, 2010
    Date of Patent: April 16, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Yamasaki, Hidemitsu Aoki
  • Patent number: 8129287
    Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: March 6, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsuya Suzuki, Hidemitsu Aoki
  • Publication number: 20110130010
    Abstract: A method of manufacturing a semiconductor device includes preparing a semiconductor wafer having a device area, an end face, and a surface peripheral area located outside the device area and between the end face and the device area. Forming a Cu layer on the semiconductor wafer and rotating the wafer in a horizontal plane. Emitting a first liquid from an edge nozzle towards the surface peripheral area which selectively removes a first unnecessary material in the surface peripheral area. Emitting a protecting liquid toward the semiconductor wafer, thereby protecting the device area from the first liquid. An angle of a longitudinal axis of the edge nozzle with respect to a tangent of the semiconductor wafer at a point, where the longitudinal axis of the edge nozzle intersects the end face of the wafer, is set in the range of 0 to 90 degrees in plan view.
    Type: Application
    Filed: November 24, 2010
    Publication date: June 2, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinya YAMASAKI, Hidemitsu AOKI
  • Patent number: 7943516
    Abstract: A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by ashing. A wafer after an ashing process is cleaned using a cleaning solution comprised of aqueous solution having a content of the fluorine-containing compound of 1.0 to 5.0 mass %, a content of chelating agent of 0.2 to 5.0 mass %, and a content of the organic acid salt of 0.1 to 3.0 mass %.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: May 17, 2011
    Assignees: Renesas Electronics Corporation, Kanto Kagaku Kabushiki Kaisha
    Inventors: Hidemitsu Aoki, Tatsuya Suzuki, Takuo Ohwada, Kaoru Ikegami, Norio Ishikawa
  • Patent number: 7862658
    Abstract: An etching/cleaning apparatus is provided, which makes it possible to effectively remove an unnecessary material or materials existing on a semiconductor wafer without damaging the device area with good controllability. The apparatus comprises (a) a rotating means for holding a semiconductor wafer and for rotating the wafer in a horizontal plane; the wafer having a device area and a surface peripheral area on its surface; the surface peripheral area being located outside the device area; and (b) an edge nozzle for emitting an etching/cleaning liquid toward a surface peripheral area of the wafer. The etching/cleaning liquid emitted from the edge nozzle selectively removes an unnecessary material existing in the surface peripheral area.
    Type: Grant
    Filed: June 6, 2005
    Date of Patent: January 4, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shinya Yamasaki, Hidemitsu Aoki
  • Patent number: 7718532
    Abstract: According to the present invention, high-k film can be etched to provide a desired geometry without damaging the silicon underlying material. A silicon oxide film 52 is formed on a silicon substrate 50 by thermal oxidation, and a high dielectric constant insulating film 54 comprising HfSiOx is formed thereon. Thereafter, polycrystalline silicon layer 56 and high dielectric constant insulating film 54 are selectively removed in stages by a dry etching through a mask of the resist layer 58, and subsequently, the residual portion of the high dielectric constant insulating film 54 and the silicon oxide film 52 are selectively removed by wet etching through a mask of polycrystalline silicon layer 56. A liquid mixture of phosphoric acid and sulfuric acid is employed for the etchant solution. The temperature of the etchant solution is preferably equal to or lower than 200 degree C., and more preferably equal to or less than 180 degree C.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: May 18, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Toshiyuki Iwamoto
  • Patent number: 7687918
    Abstract: The present invention provides a semiconductor device comprising a metal interconnect having considerably improved electromigration resistance and/or stress migration resistance. The copper interconnect 107 comprises a silicon-lower concentration region 104 and a silicon solid solution layer 106 disposed thereon. The silicon solid solution layer 106 has a structure, in which silicon atoms are introduced within the crystal lattice structure that constitutes the copper interconnect 107 to be disposed within the lattice as inter-lattice point atoms or substituted atoms. The silicon solid solution layer 106 has the structure, in which the crystal lattice structure of copper (face centered cubic lattice; lattice constant is 3.6 angstrom) remains, while silicon atoms are introduced as inter-lattice point atoms or substituted atoms.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: March 30, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yorinobu Kunimune, Mieko Hasegawa, Takamasa Itou, Takeshi Takeda, Hidemitsu Aoki
  • Patent number: 7592266
    Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.
    Type: Grant
    Filed: November 14, 2007
    Date of Patent: September 22, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Hidemitsu Aoki, Hiroaki Tomimori
  • Patent number: 7560372
    Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: July 14, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Kaoru Mikagi, Akira Furuya, Tetsuya Tao
  • Patent number: 7442652
    Abstract: A method for removing contamination on a semiconductor substrate is disclosed. The contamination contains at least one element belonging to one of 3A group, 3B group and 4A group of long-period form of periodic system of elements. The method comprises first and second process steps. The first process is wet processing the semiconductor substrate by first remover liquid that contains one of acid and alkali. The second process is wet processing the semiconductor substrate by second remover liquid that contains oxidizing reagent and one of hydrofluoric acid and salt of hydrofluoric acid.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: October 28, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Hidemitsu Aoki, Kaori Watanabe
  • Publication number: 20080248651
    Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.
    Type: Application
    Filed: June 16, 2008
    Publication date: October 9, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Tatsuya Suzuki, Hidemitsu Aoki
  • Publication number: 20080214002
    Abstract: A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by ashing. A wafer after an ashing process is cleaned using a cleaning solution comprised of aqueous solution having a content of the fluorine-containing compound of 1.0 to 5.0 mass %, a content of chelating agent of 0.2 to 5.0 mass %, and a content of the organic acid salt of 0.1 to 3.0 mass %.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 4, 2008
    Applicants: NEC ELETRONICS CORPORATION, KANTO KAGAKU KABUSHIKI KAISHA
    Inventors: Hidemitsu Aoki, Tatsuya Suzuki, Takuo Ohwada, Kaoru Ikegami, Norio Ishikawa
  • Patent number: 7402530
    Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.
    Type: Grant
    Filed: June 7, 2006
    Date of Patent: July 22, 2008
    Assignee: NEC Electronics Corporation
    Inventors: Tatsuya Suzuki, Hidemitsu Aoki
  • Patent number: 7368064
    Abstract: A method of manufacturing a semiconductor device forms an interlayer insulating film on a nickel silicide layer formed on a substrate, and forms a through hole by performing dry etching using a resist pattern, formed on the interlayer insulating film, as a mask and then removing the resist pattern by ashing. A wafer after an ashing process is cleaned using a cleaning solution comprised of aqueous solution having a content of the fluorine-containing compound of 1.0 to 5.0 mass %, a content of chelating agent of 0.2 to 5.0 mass %, and a content of the organic acid salt of 0.1 to 3.0 mass %.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 6, 2008
    Assignees: NEC Electronics Corporation, Kanto Kagaku Kabushiki Kaisha
    Inventors: Hidemitsu Aoki, Tatsuya Suzuki, Takuo Ohwada, Kaoru Ikegami, Norio Ishikawa
  • Publication number: 20080081445
    Abstract: According to the present invention, high-k film can be etched to provide a desired geometry without damaging the silicon underlying material. A silicon oxide film 52 is formed on a silicon substrate 50 by thermal oxidation, and a high dielectric constant insulating film 54 comprising HfSiOx is formed thereon. Thereafter, polycrystalline silicon layer 56 and high dielectric constant insulating film 54 are selectively removed in stages by a dry etching through a mask of the resist layer 58, and subsequently, the residual portion of the high dielectric constant insulating film 54 and the silicon oxide film 52 are selectively removed by wet etching through a mask of polycrystalline silicon layer 56. A liquid mixture of phosphoric acid and sulfuric acid is employed for the etchant solution. The temperature of the etchant solution is preferably equal to or lower than 200 degree C., and more preferably equal to or less than 180 degree C.
    Type: Application
    Filed: January 31, 2007
    Publication date: April 3, 2008
    Applicants: NEC ELECTRONICS CORPORATION, NEC CORPORATION
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Toshiyuki Iwamoto
  • Patent number: 7351354
    Abstract: A removing solution for removing tungsten metal which causes a film formation on a semiconductor substrate or adheres to it, wherein orthoperiodic acid and water are contained.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: April 1, 2008
    Assignee: Kanto Kagaku Kabushiki Kaisha
    Inventors: Toshikazu Shimizu, Kaori Watanabe, Hidemitsu Aoki
  • Publication number: 20080066779
    Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.
    Type: Application
    Filed: November 14, 2007
    Publication date: March 20, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Hidemitsu AOKI, Hiroaki TOMIMORI
  • Patent number: 7312186
    Abstract: A cleaning solution for semiconductor substrates comprising a nonionic surface active agent of the formula (1) and/or the formula (2), a chelating agent and a chelating accelerator: CH3—(CH2)l—O—(CmH2mO)n—X ??(1) wherein l, m and n independently represent a positive number, and X represents a hydrogen atom or a hydrocarbon group; CH3—(CH2)a—O—(CbH2bO)d—(CxH2xO)y—X ??(2) wherein a, b, d, x and y independently represent a positive number, b and x are different, and X represents a hydrogen atom or a hydrocarbon group.
    Type: Grant
    Filed: January 5, 2004
    Date of Patent: December 25, 2007
    Assignees: Kanto Chemical Co., Inc., NEC Electronics Corporation
    Inventors: Masayuki Takashima, Yoshiko Kasama, Hiroaki Tomimori, Hidemitsu Aoki
  • Patent number: 7312160
    Abstract: The removing solution containing a cerium (IV) nitrate salt, periodic acid or a hypochlorite can be applied to metals containing copper, silver or palladium and also to metals containing other metals having a relatively large oxidation-reduction potential.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: December 25, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Hidemitsu Aoki, Hiroaki Tomimori
  • Patent number: 7268087
    Abstract: In order to provide a manufacturing method of a semiconductor device which can improve the interconnection lifetime, while controlling the increase in resistance thereof, and, in addition, can raise the manufacturing stability; by applying a plasma treatment to the surface of a copper interconnection 17 with a source gas comprising a nitrogen element being used, a copper nitride layer 24 is formed, and thereafter a silicon nitride film 18 is formed. Hereat, under the copper nitride layer 24, a thin copper silicide layer 25 is formed.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: September 11, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Hidemitsu Aoki, Hiroaki Tomimori, Norio Okada, Tatsuya Usami, Koichi Ohto, Takamasa Tanikuni