Patents by Inventor Hidenao Kuribayashi

Hidenao Kuribayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9818852
    Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 ?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Hidenao Kuribayashi, Yuichi Onozawa, Hayato Nakano, Daisuke Ozaki
  • Patent number: 9812561
    Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 ?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 7, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Hidenao Kuribayashi, Yuichi Onozawa, Hayato Nakano, Daisuke Ozaki
  • Publication number: 20170317163
    Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Takashi YOSHIMURA, Masayuki MIYAZAKI, Hiroshi TAKISHITA, Hidenao KURIBAYASHI
  • Patent number: 9768246
    Abstract: Hydrogen atoms and crystal defects are introduced into an n? semiconductor substrate by proton implantation. The crystal defects are generated in the n? semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: September 19, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Masayuki Miyazaki, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 9735109
    Abstract: To restrict the deterioration of properties in a semiconductor device due to hydrogen, provided is a semiconductor device including a semiconductor substrate; a hydrogen absorbing layer that is provided above a top surface of the semiconductor substrate and formed of a first metal having a hydrogen absorbing property; a nitride layer that is provided above the hydrogen absorbing layer and formed of a nitride of the first metal; an alloy layer that is provided above the nitride layer and formed of an alloy of aluminum and a second metal; and an electrode layer that is provided above the alloy layer and formed of aluminum. A pure metal layer of the second metal is not provided between the electrode layer and the nitride layer.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: August 15, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hidenao Kuribayashi
  • Patent number: 9722016
    Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: August 1, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Masayuki Miyazaki, Hidenao Kuribayashi
  • Publication number: 20170170126
    Abstract: To restrict the deterioration of properties in a semiconductor device due to hydrogen, provided is a semiconductor device including a semiconductor substrate; a hydrogen absorbing layer that is provided above a top surface of the semiconductor substrate and formed of a first metal having a hydrogen absorbing property; a nitride layer that is provided above the hydrogen absorbing layer and formed of a nitride of the first metal; an alloy layer that is provided above the nitride layer and formed of an alloy of aluminum and a second metal; and an electrode layer that is provided above the alloy layer and formed of aluminum. A pure metal layer of the second metal is not provided between the electrode layer and the nitride layer.
    Type: Application
    Filed: October 28, 2016
    Publication date: June 15, 2017
    Inventor: Hidenao KURIBAYASHI
  • Publication number: 20170047408
    Abstract: A method of manufacturing a silicon carbide semiconductor device. The method includes providing an n-type semiconductor substrate having first and second principal surfaces, introducing an impurity from a first principal surface of the semiconductor substrate at a first position, activating the impurity to form a diffusion layer in the semiconductor substrate at a second position, implanting protons at a third position that is deeper from the first principal surface than the first position, the protons generating crystal defects in a region through which the protons pass, converting by thermal treating the protons into hydrogen induced donors to form an n-type field stop layer at a fourth position deeper from the first principal surface than the second position, reducing by the thermal treating the generated crystal defects to form an n-type crystal defect reduction region, and forming an electrode on the second principal surface after implanting the protons.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hidenao KURIBAYASHI, Masayuki MIYAZAKI
  • Publication number: 20170025520
    Abstract: A method of producing a semiconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.
    Type: Application
    Filed: October 7, 2016
    Publication date: January 26, 2017
    Inventors: Masayuki MIYAZAKI, Takashi YOSHIMURA, Hiroshi TAKISHITA, Hidenao KURIBAYASHI
  • Patent number: 9520475
    Abstract: A method of producing a seminconductor device is disclosed in which, after proton implantation is performed, a hydrogen-induced donor is formed by a furnace annealing process to form an n-type field stop layer. A disorder generated in a proton passage region is reduced by a laser annealing process to form an n-type disorder reduction region. As such, the n-type field stop layer and the n-type disorder reduction region are formed by the proton implantation. Therefore, it is possible to provide a stable and inexpensive semiconductor device which has low conduction resistance and can improve electrical characteristics, such as a leakage current, and a method for producing the semiconductor device.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: December 13, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki Miyazaki, Takashi Yoshimura, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 9484343
    Abstract: A method for manufacturing a semiconductor device suppresses loss of vacuum in a chamber of an ion implanter, sag of a resist mask pattern for ion implantation, and producing a resist residue after ashing. First ion implanting process implants n-type impurity to form n+ impurity layer on the whole back surface of n? semiconductor wafer. A resist mask on the back surface of the wafer covers a part corresponding to where n+ cathode layer will be formed. A second ion implanting process implants p-type impurity using the resist mask to form p+ impurity layer in the interior of the n+ impurity layer. Second ion implanting process is split into two or more times. The dose of p-type impurity in second ion implanting process is greater than that of n-type impurity in first ion implanting process. The resist mask is removed, and p+ the n+ impurity layers activated.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 1, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Seiji Noguchi, Hidenao Kuribayashi
  • Publication number: 20160307993
    Abstract: A defective layer is formed by ion implanting argon for a p+ anode layer from a front surface side of a base substrate. Here, the range of the argon is set to be shallower than the diffusion depth of the p+ anode layer such that platinum atoms are localized in an electron entering region near a pn junction of the p+ anode layer with an n? drift layer at a platinum diffusion step executed later. The platinum atoms in a platinum paste applied to the back surface of the base substrate are thereafter diffused in the p+ anode layer to be localized on a cathode side of the defective layer.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 20, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hidenao KURIBAYASHI, Shoji KITAMURA, Yuichi ONOZAWA
  • Patent number: 9466689
    Abstract: A semiconductor device includes an input electrode provided on a front surface of a semiconductor substrate of a first conductivity type and an output electrode provided on a rear surface of the semiconductor substrate. The device has reduced deterioration of electrical characteristics when manufactured by a method including introducing impurities into the rear surface of the semiconductor substrate; activating the impurities using a first annealing process to form a first semiconductor layer, which is a contact portion in contact with the output electrode, in a surface layer of the rear surface; radiating protons to the rear surface; and activating the protons radiated using a second annealing process to form a second semiconductor layer of the first conductivity type, which has a higher impurity concentration than the semiconductor substrate, in a region that is deeper than the first semiconductor layer from the rear surface of the semiconductor substrate.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: October 11, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki Miyazaki, Takashi Yoshimura, Hiroshi Takishita, Hidenao Kuribayashi
  • Publication number: 20160284796
    Abstract: A p+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n? drift layer and an n+ field stop layer is provided in a region which is deeper than the p+ collector layer formed on the rear surface side. A front surface element structure is formed on the front surface of the semiconductor substrate and then protons are radiated to the rear surface of the semiconductor substrate at an acceleration voltage corresponding to the depth at which the n+ field stop layer is formed. A first annealing process is performed at an annealing temperature corresponding to the proton irradiation to change the protons into donors, thereby forming a field stop layer. Then, annealing is performed using annealing conditions suitable for the conditions of a plurality of proton irradiation processes to recover each crystal defect formed by each proton irradiation process.
    Type: Application
    Filed: June 3, 2016
    Publication date: September 29, 2016
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki MIYAZAKI, Takashi YOSHIMURA, Hiroshi TAKISHITA, Hidenao KURIBAYASHI
  • Publication number: 20160268366
    Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 15, 2016
    Inventors: Hiroshi TAKISHITA, Takashi YOSHIMURA, Masayuki MIYAZAKI, Hidenao KURIBAYASHI
  • Patent number: 9431270
    Abstract: A method for producing a semiconductor device is disclosed which includes a diffusion step of forming, on a CZ-FZ silicon semiconductor substrate, a deep diffusion layer involving a high-temperature and long-term thermal diffusion process which is performed at a thermal diffusion temperature of 1290° C. to a melting temperature of a silicon crystal for 100 hours or more; and a giving step of giving a diffusion source for an interstitial silicon atom to surface layers of two main surfaces of the silicon semiconductor substrate before the high-temperature, long-term thermal diffusion process. The step of giving the diffusion source for the interstitial silicon atom to the surface layers of the two main surfaces of the silicon semiconductor substrate is performed by forming thermally-oxidized films on two main surfaces of the silicon semiconductor substrate or by implanting silicon ions into surface layers of the two main surfaces of the silicon semiconductor substrate.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: August 30, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Haruo Nakazawa, Masaaki Ogino, Hidenao Kuribayashi, Hideaki Teranishi
  • Publication number: 20160211356
    Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 ?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.
    Type: Application
    Filed: March 30, 2016
    Publication date: July 21, 2016
    Inventors: Takashi YOSHIMURA, Hidenao KURIBAYASHI, Yuichi ONOZAWA, Hayato NAKANO, Daisuke OZAKI
  • Publication number: 20160197170
    Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.
    Type: Application
    Filed: March 15, 2016
    Publication date: July 7, 2016
    Inventors: Takashi YOSHIMURA, Hidenao KURIBAYASHI, Yuichi ONOZAWA, Hayato NAKANO, Daisuke OZAKI
  • Patent number: 9385211
    Abstract: A p+ collector layer is provided in a rear surface of a semiconductor substrate which will be an n? drift layer and an n+ field stop layer is provided in a region which is deeper than the p+ collector layer formed on the rear surface side. A front surface element structure is formed on the front surface of the semiconductor substrate and then protons are radiated to the rear surface of the semiconductor substrate at an acceleration voltage corresponding to the depth at which the n+ field stop layer is formed. A first annealing process is performed at an annealing temperature corresponding to the proton irradiation to change the protons into donors, thereby forming a field stop layer. Then, annealing is performed using annealing conditions suitable for the conditions of a plurality of proton irradiation processes to recover each crystal defect formed by each proton irradiation process.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 5, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masayuki Miyazaki, Takashi Yoshimura, Hiroshi Takishita, Hidenao Kuribayashi
  • Patent number: 9368577
    Abstract: Proton irradiation is performed a plurality of times from rear surface of an n-type semiconductor substrate, which is an n? drift layer, forming an n-type FS layer having lower resistance than the n-type semiconductor substrate in the rear surface of the n? drift layer. When the proton irradiation is performed a plurality of times, the next proton irradiation is performed to as to compensate for a reduction in mobility due to disorder which remains after the previous proton irradiation. In this case, the second or subsequent proton irradiation is performed at the position of the disorder which is formed by the previous proton irradiation. In this way, even after proton irradiation and a heat treatment, the disorder is reduced and it is possible to prevent deterioration of characteristics, such as increase in leakage current. It is possible to form an n-type FS layer including a high-concentration hydrogen-related donor layer.
    Type: Grant
    Filed: May 13, 2014
    Date of Patent: June 14, 2016
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hiroshi Takishita, Takashi Yoshimura, Masayuki Miyazaki, Hidenao Kuribayashi