Patents by Inventor Hidenori Matsuzaki
Hidenori Matsuzaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110307667Abstract: A memory system according to an embodiment of the present invention comprises: a first management table that manages addresses concerning the data written in a first storing area; and a second management table that manages, in an address unit of a second management unit, information indicating temporal order of the data stored in the first storing area and manages, for each of addresses in a second management unit, number-of-valid-data information indicating a number of data in the first management unit included in the addresses in the second management unit.Type: ApplicationFiled: February 10, 2009Publication date: December 15, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki, Ryoichi Kato
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Patent number: 8065471Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third, and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit having the oldest allocation order in the fourth memory area to the second memory area, and a fifth processing for selecting data in the second memory area and copying the selected data to an empty area of the third unit in the second memory area.Type: GrantFiled: September 2, 2009Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 8065470Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.Type: GrantFiled: September 2, 2009Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Publication number: 20110264859Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.Type: ApplicationFiled: February 10, 2009Publication date: October 27, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Patent number: 8037277Abstract: A computer-readable storage medium stores a program for causing a processor to perform a process including: acquiring a first address that specifies a start address of a first area on the main memory where a target data to be cached is stored and range information that specifies a size of the first area on the main memory; converting the first address into a second address that specifies a start address of a second area on the local memory, the second area having a one-to-n correspondence (n=positive integer) to a part of a bit string of the first address; copying the target data stored in the first area specified by the first address and the range information onto the second area specified by the second address and the range information; and storing the second address to allow accessing the target data copied onto the local memory.Type: GrantFiled: February 28, 2008Date of Patent: October 11, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Seiji Maeda, Hidenori Matsuzaki, Yusuke Shirota, Kazuya Kitsunai
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Publication number: 20110231734Abstract: A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.Type: ApplicationFiled: June 3, 2011Publication date: September 22, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji YANO, Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira
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Publication number: 20110185108Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20110185107Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit, and a controller. The controller performs data transfer, stores management information including a storage position of the data stored in the second storing unit into the first storing unit, and performs data management while updating the management information. The second storing unit has a management information storage area for storing management information storage information including management information in a latest state and a storage position of the management information. The storage position information is read by the controller during a startup operation of the memory system and includes a second pointer indicating a storage position of management information in a latest state in the management information storage area and a first pointer indicating a storage position of the second pointer.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Shigehiro Asano, Shinichi Kanno, Toshikatsu Hida
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Publication number: 20110185105Abstract: A memory system in which speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponds to the logical address, and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position. These forward and reverse lookup tables are linked.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
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Publication number: 20110185106Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.Type: ApplicationFiled: February 10, 2009Publication date: July 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 7962688Abstract: A semiconductor storage device includes first, second, third, fourth and fifth memory areas and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the fifth memory area, a fourth processing for moving an area of the third unit to the second memory area, a fifth processing for selecting and copying data to an empty area of the third unit in the second memory area, a sixth processing for moving an area of the third unit to the third memory area, and a seventh processing for selecting and copying data to an empty area of the third unit in the third memory area.Type: GrantFiled: September 2, 2009Date of Patent: June 14, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Patent number: 7957933Abstract: An information processing apparatus includes a receptor for receiving an event signal occurring in hardware during program execution in time series, a feature event counter for counting the number of occurrences of a feature event to determine the feature of the program, a stored event counter for counting the number of occurrences of stored event determined from the feature event with the maximum number of occurrences, and a storage for storing the count result of the number of occurrences of the stored event.Type: GrantFiled: August 23, 2007Date of Patent: June 7, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuya Kitsunai, Seiji Maeda, Hidenori Matsuzaki, Yusuke Shirota
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Patent number: 7953920Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second, third and fourth memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data by a first management unit in the fourth memory area, a third processing for storing data by a second management unit in the third memory area, a fourth processing for moving an area of the third unit from the fourth memory area to the second memory area, a fifth processing for copying data to an area of the third unit and allocating the area to the second memory area, and a sixth processing for copying data to an empty area of the third unit in the second memory area.Type: GrantFiled: September 2, 2009Date of Patent: May 31, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
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Publication number: 20110099349Abstract: A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.Type: ApplicationFiled: January 4, 2011Publication date: April 28, 2011Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Patent number: 7904640Abstract: A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.Type: GrantFiled: September 22, 2008Date of Patent: March 8, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20110022784Abstract: A memory system according to an embodiment of the present invention comprises: a memory amount required for management table creation is reduced by adopting a nonvolatile semiconductor memory including a plurality of parallel operation elements respectively having a plurality of physical blocks as units of data erasing and a controller that can drive the parallel operation elements in parallel and has a number-of-times-of-erasing managing unit that manages the number of times of erasing in logical block units associated with a plurality of physical blocks driven in parallel.Type: ApplicationFiled: February 10, 2009Publication date: January 27, 2011Inventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki, Toshikatsu Hida
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Publication number: 20100312948Abstract: A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.Type: ApplicationFiled: February 10, 2009Publication date: December 9, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20100281204Abstract: A memory system includes a WC 21 from which data is read out and to which data is written in sector units by a host apparatus, an FS 12 from which data is read out and to which data is written in page units, an MS 11 from which data is read out and to which data written in track units, an FSIB 12a functioning as an input buffer for the FS 12, and an MSIB 11a functioning as an input buffer to the MS 11. An FSBB 12ac that has a capacity equal to or larger than a storage capacity of the WC 21 and stores data written in the WC 21 is provided in the FSIB12a. A data managing unit 120 that manages the respective storing units suspends, when it is judged that one kind of processing performed among the storing units exceeds predetermined time, the processing judged as exceeding the predetermined time and controls the data written in the WC 21 to be saved in the FSBB 12ac.Type: ApplicationFiled: September 22, 2008Publication date: November 4, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20100274950Abstract: A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.Type: ApplicationFiled: September 22, 2008Publication date: October 28, 2010Applicant: Kabushiki Kaisha ToshibaInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda
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Publication number: 20100153626Abstract: To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.Type: ApplicationFiled: February 10, 2009Publication date: June 17, 2010Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Junji Yano, Hidenori Matsuzaki, Kosuke Hatsuda, Hiroki Matsudaira