Abstract: A program information generating system includes an acquisition unit, a generating unit, and display control unit. The acquiring unit acquires program information which represents structure of a computer program and operation information which represents structure of operations. The generating unit generates first display information for generating a first display image which visually represents the structure of the computer program and second display information for generating a second display image which visually represents the structure of the operations. The program information includes section information which identifies a position of sections included in the computer program. The operation information includes section identification information which identifies the section corresponding to the operations.

Abstract: A system according to embodiments comprises first to third acquisition units and first and second creation units. The first acquisition unit may acquire event information including timeline information about an execution time or an execution order of at least one event. The second acquisition unit may acquire axis information including first axis information for deciding an first coordinate axis of a timeline about the execution time or the execution order of the event. The third acquisition unit may acquire event specific information for specifying the event information. The first creation unit may create a first axis object representing the first coordinate axis based on the axis information.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Abstract: A program information generating system includes an acquisition unit that acquires dependency information indicating dependency among a plurality of events generated by execution of a program and selection information identifying a selected event that is the event selected by a user; a generation unit that generates display information, on the basis of the dependency information and the selection information, such that a dependency path that is formed of the plurality of events having the dependency and includes the selected event is displayed in a distinguishable manner; and a display control unit that controls a display unit, on the basis of the display information, such that a display image indicating an execution state of the program is displayed.

Abstract: A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.

Abstract: A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: A memory system according to an embodiment of the present invention comprises: speed of processing for searching through management tables is increased by providing a forward lookup table for searching for, respectively in track and cluster units, from a logical address, a storage device position where data corresponding to the logical address and a reverse lookup table for searching for, from a position of the storage device, a logical address stored in the position and linking these tables.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

Abstract: A memory system includes a controlling unit that configured to control data transfer between the first and the second memory. The controlling unit executes copy processing for, after reading out data stored in a first page of the second memory to the first memory, writing the data in a second page of the second memory, determines, when executing the copy processing, whether the error correction processing for the data read out from the first page is successful, stores, when the error correction processing is successful, corrected data in the first memory and writes the corrected data in the second page, and reads out, when the error correction processing is unsuccessful, the data from the first page to the first memory and writes the data not subjected to the error correction processing in the second page.

Abstract: A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.

Abstract: A memory system includes a management-information restoring unit. The management-information restoring unit determines whether a short break has occurred referring to a pre-log or a post-log in a NAND memory. The management-information restoring unit determines that a short break has occurred when the pre-log or the post-log is present in the NAND memory. In that case, the management-information restoring unit determines timing of occurrence of the short break, and, after selecting a pre-log or a post-log used for restoration, performs restoration of the management information reflecting these logs on a snapshot. Thereafter, the management-information restoring unit applies recovery processing to all write-once blocks in the NAND memory, takes the snapshot again, and opens the snapshot and the logs in the past.

Abstract: A trace generating unit according to an embodiment of the present invention generates parallel trace information by executing a sequential program code, in case that the above-described sequential program code is parallelized and executed. The sequential program code includes a plurality of processing codes, codes to record a start and an end of the execution for each processing code, and codes to record a start and an end of the execution for each thread. The parallel trace information includes an execution sequence of the threads and an execution sequence of the processing codes for each thread.

Abstract: According to an embodiment, an information processing apparatus includes a storage, an accepting unit, an analyzer, a determination unit, and an output controller. The storage stores therein one or more pieces of first feature information respectively representing features of one or more source codes, and one or more pieces of assistance information representing update situations of the source codes, in a corresponding manner. The accepting unit accepts input of second feature information representing a feature of a source code to be analyzed. The analyzer calculates similarity between the first feature information and the second feature information. The determination unit selects, based on the similarity, assistance information to be output, from the pieces of assistance information stored in the storage. The output controller outputs the selected assistance information.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: A system according to an embodiment may include: a generation unit that acquires axis information in a coordinate system drawing execution status of a program, and generates an axis object representing the coordinate system based on the axis information; a display event information generation unit that acquires event information related to each of the two or more events and program structure information related to a section of the program generating the two or more events, and generates display event information related to one or more display events representing the two or more events; and an object generation unit that acquires the display event information and display event unit information indicating a display unit of the display event, and generates one or more event objects based on the display event information and the display event unit information.

Abstract: A system according to an embodiment is configured to display program execution results with respect to a common axis. The system includes a first unit that acquires event information about two or more events, acquires reference-event identification information to be used in identifying reference events, and generates event objects which represent the events, and a second unit that acquires axis information which represents information about the common axis. The event information contains timing information indicating positions of the events. The first unit sets the reference events as references for the program execution results based on the acquired reference-event identification information, determines display positions of the reference events with respect to the common axis to be same position based on timing information in event information about the reference events, and generates event objects representing the reference events based on the determined display positions with respect to the common axis.

Abstract: In a system according to any one of embodiments, program structure information may include interval information. Each interval information may include source code position information indicating a successive region on a source code of a target program and parent-child information for specifying a parent-child relationship with respect to the interval information. The program structure information may include a reference interval without a parent. A processing unit may specify the number of parents existing between each interval information and the reference interval as a depth of each interval information from the reference interval, and create display information by arranging the interval information on a coordinate system defined by a first axis representing depth from the reference interval and a second axis representing the parent-child relationship based on the depth from the reference and the parent-child information.

Abstract: A memory system includes a nonvolatile semiconductor memory having blocks, the block being data erasing unit; and a controller configured to execute; an update processing for; writing superseding data in a block, the superseding data being treated as valid data; and invalidating superseded data having the same logical address as the superseding data, the superseded data being treated as invalid data; and a compaction processing for; retrieving blocks having invalid data using a management table, the management table managing blocks in a linked list format for each number of valid data included in the block; selecting a compaction source block having at least one valid data from the retrieved blocks; copying a plurality of valid data included in the compaction source blocks into a compaction target block; invalidating the plurality of valid data in the compaction source blocks; and releasing the compaction source blocks in which all data are invalidated.