Abstract: A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.

Abstract: A memory system includes a management table group in which management information including storage positions of data stored in a first storing area and a second storing area is stored. The management table group is stored in the second storing area. A controller performs data transfer between a host apparatus and the second storing area via the first storing area and performs management of the data in the first and second storing areas based on the management table group while updating the management table group expanded in the first storing area. The second storing area can store data associated with a first logical address area accessible from the host apparatus and data associated with a second logical address area accessible from the host apparatus, and the controller receives an erasing command from the host apparatus, collects the data associated with the second logical address area in a predetermined area in the second storing area, and then initializes the management table group.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: An order-relation analyzing apparatus collects assigned destination processor information, a synchronization process order and synchronization information, determines a corresponding element associated with a program among a plurality of elements indicating an ordinal value of the program based on the assigned destination processor information, when an execution of the program is started, and calculates the ordinal value indicated by the corresponding element for each segment based on the synchronization information, when the synchronization process occurs while executing the program. When a first corresponding element associated with a second program, of which the execution starts after the execution of a first program associated with the first corresponding element finishes, is determined, the ordinal value of the second program is calculated by calculating the ordinal value indicated by the first corresponding element.

Abstract: A memory system includes a nonvolatile memory including a plurality of blocks, a volatile memory storing management information including a storage position of data stored in the nonvolatile memory, a management information writing unit, and a management information storing unit. The management information writing unit is configured to update, when the storage position of data is changed in the nonvolatile memory, the management information stored in the volatile memory. The management information storing unit is configured to, before writing data to the nonvolatile memory, store a first log including an update schedule of the management information in the nonvolatile memory and, after writing data to the nonvolatile memory, store a second log including an update result of the management information in the nonvolatile memory, wherein the management information storing unit is configured to store the first log and the second log in the same-numbered page of the different two blocks.

Abstract: A memory system includes a controller that manages data stored in the first and second storing areas. The controller determines, when a readout error occurs when the stored data in the second storing area is read out, success or failure of error correction to the read-out data based on the result of the error correction stored in a storage buffer, writes, when the error correction is successful, correction data corresponding to the read-out data stored in the storage buffer, and writes, when the error correction fails, the read-out data itself not subjected to error correction processing.

Abstract: A compiler device 10 includes: an input unit inputting a data flow graph including a set of nodes and a set of edges and information indicating a range of values that can be taken by data flowing along each edge; and a determination unit determining, from among a plurality of different types of hardware resources, a hardware resource to which a first node can be assigned based on the first node type and information indicating the range of values that can be taken by data flowing along a first edge connected to the first node. The compiler device 10 makes it possible to efficiently utilize hardware resources without losing data accuracy.

Abstract: A memory system includes a controller that reads out, data written in a nonvolatile second storing area, from which data is read out and in which data is written in a page unit, to a first storing area as a cache memory included in a semiconductor memory and transfers the data to the host apparatus. The controller performs, when a readout request from the host apparatus satisfies a predetermined condition, at least one of first pre-fetch for reading out, to the first storing area data from a terminal end of a logical address range designated by a readout request being currently processed to a boundary of a logical address aligned in the page unit and a second pre-fetch for reading out data from the boundary of the logical address aligned in the page unit to a next boundary of the logical address.

Abstract: According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output.

Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.

Abstract: A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which a plurality of memory cells that can store multi-value data are arranged, the memory cells having a plurality of pages, and a controller that performs data transfer between a host apparatus and the second storing unit via the first storing unit. The controller includes a save processing unit that backs up, when, before data is written in the second storing unit in a write-once manner, data is written in a lower order page of a memory cell same as that of a page in which the data is written, the data of the lower order page and a broken-information-restoration processing unit that restores, when the data in the lower order page is broken, the broken data using the backed-up data.

Abstract: A memory system according to an embodiment of the present invention comprises: a data managing unit 120 is divided into a DRAM-layer managing unit 120a, a logical-NAND-layer managing unit 120b, and a physical-NAND-layer managing unit 120c to independently perform management of a DRAM layer, a logical NAND layer, and a physical NAND layer using the respective managing units to thereby perform efficient block management.

Abstract: A controller executes first processing for writing a plurality of data in a sector unit in the first storing area; second processing for flushing the data stored in the first storing area to the first input buffer in a first management unit twice or larger natural number times as large as the sector unit; third processing for flushing the data stored in the first storing area to the second input buffer in a second management unit twice or larger natural number times as large as the first management unit; fourth processing for relocating a logical block in which all pages are written in the first input buffer to the second storing area; fifth processing for relocating a logical block in which all pages are written in the second input buffer to the third storing area; and sixth processing for flushing a plurality of data stored in the second storing area to the second input buffer in the second management unit.

Abstract: A memory system includes a DRAM 20 that performs writing and readout in a unit equal to or smaller than a cluster, a NAND memory 10 that performs writing and readout in a page unit, and a management table group in which management information including storage locations of data stored in the DRAM 20 and the NAND memory 10 is stored. When a readout request is received from the outside, a data managing unit 120 notifies, when an unwritten logical address area is present in a storage area of the NAND memory to which a logical address area requested to be read out is mapped, fixed data stored in the DRAM 20 to the outside in association with the logical address area.

Abstract: According to one embodiment, a parallelizing unit divides a loop into first and second processes based on a program to be converted and division information. The first and second processes respectively have termination control informationloop control information and change information indicating change of data to be referred to in a process subsequent to the loop. The parallelizing unit inserts a determination process into the first process, which determines whether the second process is terminated at execution of an (n?1)th iteration of the second process when the second process is subsequent to the first process, or determines whether the second process is terminated at execution of an nth iteration of the second process when the second process precedes the first process, and notifies the second process of a result of the determination, and inserts a control process into the second process, which controls execution of the second process based on the result of determination notified.

Abstract: A trace generating unit according to an embodiment of the present invention generates parallel trace information by executing a sequential program code, in case that the above-described sequential program code is parallelized and executed. The sequential program code includes a plurality of processing codes, codes to record a start and an end of the execution for each processing code, and codes to record a start and an end of the execution for each thread. The parallel trace information includes an execution sequence of the threads and an execution sequence of the processing codes for each thread.

Abstract: According to one embodiment, as to a first program code including a plurality of variables, an access pattern of each variable by a processor is decided. The first program code is converted to a second program code including a plurality of threads. Each thread is executed by one of a plurality of cores of the processor. The second program code includes, (a) a first member structure including variables decided as a first access pattern, (b) a first route-pointer indicating the first member structure, the first route-pointer having a first access property representing accessibility by a core to execute a first thread, (c) a second member structure including variables decided as a second access pattern, (d) a second route-pointer indicating the second member structure, the second route-pointer having a second access property representing accessibility by the core to execute the first thread and a core to execute a second thread.

Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.

Abstract: To provide a memory system that can surely restore management information even when a program error occurs during data writing. After “log writing (1)” for a pre-log, when a program error occurs when data writing is being performed (a data writing error), the memory system performs the data writing again without acquiring a pre-log corresponding to data rewriting processing. After finishing the data writing, the memory system acquires, without generating a post-log, a snapshot instead of the post-log and finishes the processing.

Abstract: A system includes: a first input buffer that functions as an input buffer for a third storing area; and a second input buffer that functions as an input buffer for the third storing area and that separately stores data with a high update frequency for the third storing area. In the system, a plurality of data written in a first storing area or a second storing area are flushed to the first input buffer in units of logical blocks. Also, a plurality of data written in the first input buffer are relocated to the third storing area in units of logical blocks.