Patents by Inventor Hideo Aizawa
Hideo Aizawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20120066569Abstract: A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.Type: ApplicationFiled: November 14, 2011Publication date: March 15, 2012Inventor: Hideo AIZAWA
-
Patent number: 8078941Abstract: A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.Type: GrantFiled: January 31, 2007Date of Patent: December 13, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Hideo Aizawa
-
Patent number: 7739443Abstract: The present invention provides a memory controller which includes a host interface connected to a host apparatus and receives a first data write-in unit of reception data, a memory interface connected to nonvolatile semiconductor memory in which is written a second data write-in unit of data larger than the first data write-in unit of data, and transmits the first data write-in unit of write-in data, and a central processing unit, which writes the reception data in a temporary write-in block of the nonvolatile semiconductor memory via the memory interface, reads out from the temporary write-in block the write-in data corresponding to area data when a total amount of reception data received by the host interface has reached amount of the second data write-in unit of the area data, and writes the area data including the read-out write-in data in a target block different from the temporary write-in block.Type: GrantFiled: September 21, 2005Date of Patent: June 15, 2010Assignee: Kabushiki Kaisha ToshibaInventor: Hideo Aizawa
-
Patent number: 7645185Abstract: A substrate delivery mechanism comprises a top ring, a substrate loader for loading a substrate, and a pusher mechanism, wherein the substrate loader comprises a top ring guide and the pusher mechanism comprises a top ring guide lifting table, in which the top ring guide and the top ring guide lifting table together form a sealed space below the substrate held by the top ring in a condition where the substrate loader is moved up by the pusher mechanism, wherein the substrate is detached from the top ring by exhausting the sealed space while at the same time injecting a fluid from through-holes provided in a substrate holding surface of the top ring.Type: GrantFiled: July 17, 2007Date of Patent: January 12, 2010Assignee: Ebara CorporationInventors: Soichi Isobe, Hideo Aizawa, Hiroomi Torii, Daisuke Koga, Satoshi Wakabayashi
-
Publication number: 20090247057Abstract: The present invention provides a polishing platen which does not require a large force for removing a polishing pad from an upper surface of the polishing platen and can thus make it relatively easy to remove the polishing pad therefrom. The present invention also provides a polishing apparatus having such polishing platen. The polishing platen (12) according to the present invention includes a surface to which a polishing pad is attached. The surface of the polishing platen (12) includes a combination of a first surface (20) and a second surface (21) having a surface roughness which is different from that of the first surface (20).Type: ApplicationFiled: September 12, 2006Publication date: October 1, 2009Inventors: Takuji Kobayashi, Hideo Aizawa, Masao Umemoto, Tadakazu Sone, Hiroomi Torii, Nobuyuki Takahashi, Takashi Tsuzuki
-
Patent number: 7529098Abstract: An electronic card includes a printed circuit board which has a nonvolatile semiconductor memory mounted on one surface thereof, a card case covering the one surface of the printed circuit board, signal pins provided in one side on the other surface of the printed circuit board, a circuit pattern provided on the one surface of the printed circuit board, a first ground pattern provided on the one surface of the printed circuit board, the first ground pattern being electrically connected to the signal pin which is supplied with a grounding potential in a case where the electronic card is equipped with a host apparatus and a first insulator film provided on the one surface of the printed circuit board, and the first insulator film having a first opening in which the first ground pattern is exposed.Type: GrantFiled: September 30, 2005Date of Patent: May 5, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Hideo Aizawa
-
Patent number: 7502970Abstract: A memory device comprises a data storage section, a section which compares in write processing, for data being target of the write processing, a state before the data is stored in the data storage section with a state of the data which is stored in the data storage section and read out from the data storage section, a section which obtains the number of errors for the write processing on the basis of a comparison result from the comparison section, and a section which returns the number of errors.Type: GrantFiled: July 14, 2004Date of Patent: March 10, 2009Assignee: Kabushiki Kaisha ToshibaInventor: Hideo Aizawa
-
Publication number: 20090025897Abstract: An object of the present invention is to provide an inorganic board lighter in weight and excellent in strength and rigidity, and a method of producing the inorganic board. An inorganic board described in claim 1 for accomplishing the object comprises a hydraulic inorganic material, an inorganic lightweight material, a woody reinforcing material and a calcium silicate hydrate, wherein a ratio of the calcium silicate hydrate to the hydraulic inorganic material is 3-54 parts by mass: 100 parts by mass. Thus, by making an inorganic board, made of a hydraulic inorganic material, an inorganic lightweight material and a woody reinforcing material as main components, further contain a calcium silicate hydrate, an inorganic board which is lightweight and excellent in strength and rigidity can be obtained.Type: ApplicationFiled: July 26, 2007Publication date: January 29, 2009Applicant: NICHIHA CO., LTD.Inventor: Hideo Aizawa
-
Publication number: 20080086967Abstract: The present invention relates to an anti-seismic reinforced structure of a building, and particularly to a fiber reinforced cement siding and an anti-seismic reinforced structure of a building using the fiber reinforced cement siding for improving moisture transmission performance by using a structural face material such as a fiber reinforced cement external wall material and the like in a wooden building.Type: ApplicationFiled: September 20, 2007Publication date: April 17, 2008Applicant: NICHIHA CO., LTDInventors: Mio Namba, Katsutoshi Sakurai, Teruyuki Kato, Hideo Aizawa, Shin Takami
-
Publication number: 20070264914Abstract: A substrate delivery mechanism comprises a top ring, a substrate loader for loading a substrate, and a pusher mechanism, wherein the substrate loader comprises a top ring guide and the pusher mechanism comprises a top ring guide lifting table, in which the top ring guide and the top ring guide lifting table together form a sealed space below the substrate held by the top ring in a condition where the substrate loader is moved up by the pusher mechanism, wherein the substrate is detached from the top ring by exhausting the sealed space while at the same time injecting a fluid from through-holes provided in a substrate holding surface of the top ring.Type: ApplicationFiled: July 17, 2007Publication date: November 15, 2007Inventors: Soichi Isobe, Hideo Aizawa, Hiroomi Torii, Daisuke Koga, Satoshi Wakabayashi
-
Publication number: 20070251265Abstract: A piping structure for a refrigerant cycle device includes an inner heat exchanger, and a bypass pipe through which refrigerant flows while bypassing the inner heat exchanger. The inner heat exchanger has a first flow passage in which high-pressure refrigerant before being decompressed flows and a second flow passage in which low-pressure refrigerant after being decompressed flows. The refrigerant cycle device includes plural low-pressure side heat exchangers, and the plural low-pressure side heat exchangers are located such that refrigerant from a part of the low-pressure side heat exchangers flows through the second flow passage of the inner heat exchanger, and refrigerant from the other part of the low-pressure side heat exchangers flows through the bypass pipe while bypassing the inner heat exchanger.Type: ApplicationFiled: April 23, 2007Publication date: November 1, 2007Applicant: DENSO CorporationInventors: Shun Kurata, Hideo Aizawa, Takahisa Suzuki
-
Publication number: 20070234142Abstract: A memory system includes code data generating section which generates code data based on write data. A nonvolatile semiconductor memory stores the write data and the code data for the write data and outputs read data and the code data for the read data. An error correcting section is configured to correct an error bit included in the read data using the read data and the code data for the read data, and outputs the read data which includes the error bit in accordance with a setting. An interface section receives the write data from outside of the memory system, and outputs the read data to outside of the memory system.Type: ApplicationFiled: January 31, 2007Publication date: October 4, 2007Inventor: Hideo Aizawa
-
Publication number: 20070093186Abstract: A substrate delivery mechanism comprises a top ring, a substrate loader for loading a substrate, and a pusher mechanism, wherein the substrate loader comprises a top ring guide and the pusher mechanism comprises a top ring guide lifting table, in which the top ring guide and the top ring guide lifting table together form a sealed space below the substrate held by the top ring in a condition where the substrate loader is moved up by the pusher mechanism, wherein the substrate is detached from the top ring by exhausting the sealed space while at the same time injecting a fluid from through-holes provided in a substrate holding surface of the top ring.Type: ApplicationFiled: November 22, 2006Publication date: April 26, 2007Inventors: Soichi Isobe, Hideo Aizawa, Hiroomi Torii, Daisuke Koga, Satoshi Wakabayashi
-
Patent number: 7207864Abstract: The present invention relates to a polishing apparatus for polishing a workpiece, such as a semiconductor wafer, to a flat mirror finish. The polishing apparatus comprises a polishing table having a polishing surface, and a top ring, and the workpiece is interposed between the polishing table and the top ring and pressed at a predetermined pressure to polish the workpiece. The polishing apparatus comprises at least two dressing units for dressing the polishing surface by being brought into contact with the polishing surface, which is a surface of a polishing cloth.Type: GrantFiled: March 23, 2006Date of Patent: April 24, 2007Assignee: Ebara CorporationInventors: Kenji Kamimura, Norio Kimura, Satoshi Okamura, Hideo Aizawa, Makoto Akagi, Katsuhiko Tokushige, Hisanori Matsuo, Manabu Tsujimura
-
Patent number: 7160180Abstract: A substrate delivery mechanism comprises a top ring, a substrate loader for loading a substrate, and a pusher mechanism, wherein the substrate loader comprises a top ring guide and the pusher mechanism comprises a top ring guide lifting table, in which the top ring guide and the top ring guide lifting table together form a sealed space below the substrate held by the top ring in a condition where the substrate loader is moved up by the pusher mechanism, wherein the substrate is detached from the top ring by exhausting the sealed space while at the same time injecting a fluid from through-holes provided in a substrate holding surface of the top ring.Type: GrantFiled: May 5, 2006Date of Patent: January 9, 2007Assignee: Ebara CorporationInventors: Soichi Isobe, Hideo Aizawa, Hiroomi Torii, Daisuke Koga, Satoshi Wakabayashi
-
Publication number: 20060199478Abstract: A substrate delivery mechanism comprises a top ring, a substrate loader for loading a substrate, and a pusher mechanism, wherein the substrate loader comprises a top ring guide and the pusher mechanism comprises a top ring guide lifting table, in which the top ring guide and the top ring guide lifting table together form a sealed space below the substrate held by the top ring in a condition where the substrate loader is moved up by the pusher mechanism, wherein the substrate is detached from the top ring by exhausting the sealed space while at the same time injecting a fluid from through-holes provided in a substrate holding surface of the top ring.Type: ApplicationFiled: May 5, 2006Publication date: September 7, 2006Inventors: Soichi Isobe, Hideo Aizawa, Hiroomi Torii, Daisuke Koga, Satoshi Wakabayashi
-
Publication number: 20060194521Abstract: The present invention relates to a polishing apparatus for polishing a workpiece, such as a semiconductor wafer, to a flat mirror finish. The polishing apparatus comprises a polishing table having a polishing surface, and a top ring, and the workpiece is interposed between the polishing table and the top ring and pressed at a predetermined pressure to polish the workpiece. The polishing apparatus comprises at least two dressing units for dressing the polishing surface by being brought into contact with the ppolishing surface, which is a surface of a polishing cloth.Type: ApplicationFiled: March 23, 2006Publication date: August 31, 2006Inventors: Kenji Kamimura, Norio Kimura, Satoshi Okamura, Hideo Aizawa, Makoto Akagi, Katsuhiko Tokushige, Hisanori Matsuo, Manabu Tsujimura
-
Patent number: 7083506Abstract: A polishing apparatus comprises a polishing table having a polishing surface thereon, a top ring for pressing a workpiece to be polished against the polishing surface, and a dresser for dressing the polishing surface on the polishing table. The dresser comprises a dressing element provided on a surface of the dresser for dressing the polishing surface by sliding contact with the polishing surface, and an ejection nozzle provided on the surface of the dresser for ejecting a fluid supplied from a fluid source toward the polishing surface.Type: GrantFiled: July 21, 2004Date of Patent: August 1, 2006Assignee: Ebara CorporationInventors: Hiroomi Torii, Hideo Aizawa, Soichi Isobe
-
Patent number: 7063598Abstract: A substrate delivery mechanism comprises a top ring, a substrate loader for loading a substrate, and a pusher mechanism, wherein the substrate loader comprises a top ring guide and the pusher mechanism comprises a top ring guide lifting table, in which the top ring guide and the top ring guide lifting table together form a sealed space below the substrate held by the top ring in a condition where the substrate loader is moved up by the pusher mechanism, wherein the substrate is detached from the top ring by exhausting the sealed space while at the same time injecting a fluid from through-holes provided in a substrate holding surface of the top ring.Type: GrantFiled: March 27, 2003Date of Patent: June 20, 2006Assignee: Ebara CorporationInventors: Soichi Isobe, Hideo Aizawa, Hiroomi Torii, Daisuke Koga, Satoshi Wakabayashi
-
Patent number: RE40147Abstract: Disclosed herein is a card having a controller and a clock control circuit. The controller incorporates a core logic, and the clock control circuit incorporates a PLL. When a card becomes idle to wait for commands, the clock control circuit stops the supply of a clock signal to the core logic. The clock control circuit can operate in two clock control modes. In the first clock control mode, the circuit stops the PLL. In the second clock control mode, the circuit shuts off the clock signal to be supplied from the PLL to the controller.Type: GrantFiled: June 17, 2004Date of Patent: March 11, 2008Assignee: Kabushiki Kaisha ToshibaInventor: Hideo Aizawa