Abstract: A method of manufacturing a semiconductor integrated circuit device is provided including forming a first insulating film comprised of fluorine-containing silicon oxide over a main surface of a semiconductor substrate is formed together with forming a second insulating film comprising silicon oxide as a major component, forming a third insulating film comprising silicon carbide as a major component, and forming a fourth insulating film comprised of fluorine-containing silicon oxide. The fourth insulating film is removed at a wiring groove-forming region thereof by dry etching using a first photoresist film as a mask. A first conductive layer is buried inside the wiring groove and the first conductive layer is removed from outside of the wiring groove by a chemical mechanical polishing method, thereby forming a first wiring including the first conductive layer inside the wiring groove.

Abstract: A service system in which a server offers a service in response to a request from a client. The system can offer the stable service even in the case of an access from the client and also can offer a preferential service under certain conditions. The request from the client to the server is carried out via a data communication forwarding apparatus, the apparatus has a unit for queuing the request with a priority and has a unit for changing the forwarding sequence of the request according to the priority. Thereby the number of simultaneous requests to the server can be suppressed to within the processing ability of the server with the stable service. Further, the request can be preferentially processed according to the user, transaction, wait time, etc.

Abstract: In an intermediate transfer part (100), a bead 107 is formed on an inner side of an intermediate transfer belt (102), which is rotated by an intermediate transfer belt drive roller (101). Driven roller bearings (104a, 104b) support an intermediate transfer belt driven roller (103). The intermediate transfer belt driven roller (103) is movable in a thrust direction. Ends of the intermediate transfer belt driven roller (101) and the intermediate transfer belt driven roller (103) interfere with a bead (107) so as to restrict a deflection of the intermediate transfer belt in the thrust direction. The intermediate transfer belt driven roller (103) is movable in the thrust direction against a deflection of the intermediate transfer belt (102).

Abstract: The semiconductor device is formed according to the following steps. A TiN film 71 and a W film 72 are deposited on a silicon oxide film 64 including the inside of a via-hole 66 by the CVD method and thereafter, the W film 72 and TiN film 71 on the silicon oxide film 64 are etched back to leave only the inside of the via-hole 66 and form a plug 73. Then, a TiN film 74, Al-alloy film 75, and Ti film 76 are deposited on the silicon oxide film 64 including the surface of the plug 73 by the sputtering method and thereafter, the Ti film 76, Al-alloy film 75, and TiN film 74 are patterned to form second-layer wirings 77 and 78.

Abstract: The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.

Abstract: A first plating foundation layer is formed by printing on a front face of a sheet-shaped insulating substrate. By inserting a punch into the sheet-shaped insulating substrate having the first plating foundation layer, a through hole is formed while leaving a piece having the plating foundation layer in the portion where the punch is inserted. A second plating foundation layer is formed by printing on a rear face of the sheet-shaped insulating substrate. A first and second wiring layers composed of a metal plating layer are formed by performing electroless plating, and at the same time, a metal plating layer connecting between the first and second wiring layers is formed in the through hole using the plating foundation layer on the piece.

Abstract: A semiconductor integrated circuit device has a semiconductor substrate, an interlayer insulating film including SiOF films formed on a main surface of the semiconductor substrate, a wiring groove formed by dry etching of the interlayer insulating film, and a Cu wiring buried in the wiring groove by a Damascene method, wherein a silicon oxynitride film is provided between a silicon nitride film serving as an etching stopper layer for the dry etching and the SiOF film, so that free F generated in the SiOF film is trapped with the silicon oxynitride film.

Abstract: According to an embodiment of the present invention, a method of producing an electronic circuit comprises printing first metal-containing resin particles which consist of at least a thermosetting resin and fine metal particles and second metal-containing resin particles which consist of at least a thermoplastic resin and fine metal particles by electrophotography to form a first base pattern which consists of the first metal-containing resin particles and a second base pattern which consists of the second metal-containing resin particles on a substrate; forming a first metal conductor layer on the first and second base patterns; forming a second metal conductor layer on the first metal conductor layer by electrolytic plating by supplying electric current to the first metal conductor layer; and removing the second base pattern and the first and second metal conductor layers which are formed on the second base pattern.

Abstract: A wafer supporting plate is formed of a glass or a resin which can permeate ultraviolet rays and has a nearly disk shape. An outer diameter of the wafer supporting plate is larger than that of the semiconductor wafer which is supported. In the wafer supporting plate, a plurality of openings are formed to correspond to plural through holes of the semiconductor wafer. The opening has an open area larger than an open area of the through hole, that is, has a larger diameter.

Abstract: The present invention provides a thermoplastic resin composition comprising a thermoplastic resin (A), an acrylic polymer (B), a polytetrafluoroethylene-containing powder mixture (C) and a filler (D), the amount of the acrylic polymer (B) being from 0.1 to 400 parts by weight, the amount of the filler (D) being from 1 to 2000 parts by weight, based on 100 parts by weight of the thermoplastic resin (A), and the amount of a polytetrafluoroethylene component in the polytetrafluoroethylene-containing powder mixture (C) is from 0.01 to 400 parts by weight based on 100 parts by weight of the thermoplastic resin (A).

Abstract: A semiconductor device which is compact and thin in size, low in resistance of a current path and parasitic inductance and excellent in reliability is provided. This semiconductor device comprises a semiconductor substrate, a first main electrode which is formed on a front surface of the semiconductor substrate, a second main electrode which is formed on a rear surface of the semiconductor substrate, and a conducting portion which is formed in a direction to pierce through the semiconductor substrate, wherein the second main electrode is extracted to the front surface of the semiconductor substrate via the conducting portion. And, the conducting portion is a through via which has a through hole formed through the semiconductor substrate in its thickness direction and a conductive portion which is formed in the through hole and connected to the second main electrode.

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract: A semiconductor device comprises a semiconductor substrate having an through hole, a first insulation resin layer formed on an inner surface of the through hole, a second insulation resin layer formed on at least one of front and rear surfaces of the semiconductor substrate, and a first conductor layer formed in the through hole to connect at least both front and rear surfaces of the semiconductor substrate and insulated from the inner surface of the through hole with the first insulation resin layer. A second conductor layer (wiring pattern) which is electrically connected to the first conductor layer in the through hole is further provided on the second insulation resin layer. The conductor layer formed in the through hole and constituting a connecting plug has a high insulation reliability. Therefore, a semiconductor device suitable for a multi-chip package and the like can be obtained.

Abstract: In a semiconductor integrated circuit device having plural layers of buried wirings, it is intended to prevent the occurrence of a discontinuity caused by stress migration at an interface between a plug connected at a bottom thereof to a buried wiring and the buried wiring. For example, in the case where the width of a first Cu wiring is not smaller than about 0.9 ?m and is smaller than about 1.44 ?m, and the width of a second Cu wiring and the diameter of a plug are about 0.18 ?m, there are arranged two or more plugs which connect the first wirings and the second Cu wirings electrically with each other.

Abstract: A congestion control and avoidance method including a method check step of determining whether the request contents is cacheable or uncacheable on the basis of the request inputted from the client terminal, a first Uniform Resource Identifier (URI) check step of, when it is determined that the request contents is cacheable in the method check step, checking a URI included in the request from the client terminal to determine whether the request contents is cacheable or uncacheable, a first URI hash search step of, when it is determined that the request contents is cacheable based on determination of the first URI check step, searching a URI hash to determine to execute any of regular caching, priority caching and access limitationing operation, and a step of executing any of the regular caching, priority caching and access limitationing operation according to determination in the first URI hash search step.

Abstract: An image forming apparatus is disclosed that includes a substantially flat top face and a slanted front face, the bottom side of which recedes backward. The image forming apparatus may includes a paper discharge tray disposed at a lower portion of the slanted front face, the paper discharge tray protruding forward. The paper discharge tray may be tiltable upward and downward. Because the bottom side of the slanted front face recedes backward, the flat top face can be provided, and simultaneously, enough space for the feeding and discharging of paper can be secured.

Abstract: In a process for manufacturing a semiconductor integrated circuit device having a MISFET, in order that a shallow junction between the source/drain of the MISFET and a semiconductor substrate may be realized by reducing the number of heat treatment steps, all conductive films to be deposited on the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed. Moreover, all insulating films to be deposited over the semiconductor substrate are deposited at a temperature of 500° C. or lower at a step after the MISFET has been formed.

Abstract: An organic semiconductor element comprises an organic semiconductor layer and an electrode supplying an electric current or an electric field to the organic semiconductor layer. The organic semiconductor layer includes a heat fusion layer of organic semiconductor particles. The heat fusion layer of the organic semiconductor particles is formed in such a manner that, for example, the organic semiconductor particles are made to adhere on a layer that is to be a base, by using an electrophotographic method, and thereafter, an adhesion layer of the organic semiconductor particles is heated to fusion bond the organic semiconductor particles. According to such an organic semiconductor element and a manufacturing method thereof, it is possible to enhance element manufacturing efficiency without an advantage of low cost and a miniaturization of an element structure.

Abstract: A method of manufacturing an electronic circuit satisfying demands for cost reduction, diversified small-quantity production, and a shorter cycle of design, manufacture, evaluation, correction, and so on is provided. The method includes at least forming a first pattern or forming a second pattern. Forming the first pattern comprises: forming a visible image on an electrostatic latent image formed on a photosensitive base, by the adhesion of charged particles essentially made of a resin; transferring the visible image onto the intermediate transfer base by the contact and pressurization of the visible image; heating/softening on the intermediate transfer base; and transferring a heated/softened resin layer onto a base material by the contact and pressurization of the resin layer.

Abstract: A DRAM has, in one embodiment, a plurality of word lines each having its upper and side surfaces covered with a first insulating film, a plurality of bit lines each being provided so as to be insulated from and transverse to the word lines and being covered with a second insulating film, and a plurality of memory cells each provided at an intersection between one word line and one bit line and including a capacitor and a memory cell selection transistor, in which contact holes for connection between semiconductor regions and capacitors and between semiconductor regions and bit lines are formed in self-alignment and the second insulating film is made of a material having a permittivity smaller than that of the first insulating film.