Patents by Inventor Hideo Ohno

Hideo Ohno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160247550
    Abstract: A magnetoresistive device includes a magnetic free layer having first and second surfaces, the magnetic free layer being comprised of a ferromagnetic material having a perpendicular magnetic anisotropy, a spin current generation layer contacting the first surface of the magnetic free layer, a tunnel barrier layer having one surface contacting the second surface of the magnetic free layer, a reference layer contacting another surface of the tunnel barrier layer, and a leakage field generation layer including first and second leakage field generation layers each of which is comprised of a ferromagnetic material and generates a leakage field, an in-plane component of the leakage field at an part of the magnetic free layer is formed generating a domain wall having an in-plane magnetization component in the magnetic free layer.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Applicants: NEC CORPORATION, TOHOKU UNIVERSITY
    Inventors: Shunsuke FUKAMI, Michihiko YAMANOUCHI, Hideo OHNO
  • Publication number: 20160233416
    Abstract: A magnetoresistance effect element and a magnetic memory having thermal stability expressed by a thermal stability factor of 70 or more even with a fine junction size. The magnetoresistance effect element includes a first magnetic layer of an invariable magnetization direction forming a reference layer, a second magnetic layer of a variable magnetization direction forming a recording layer, and a first non-magnetic layer disposed between the first and second magnetic layers in a thickness direction of the first and second magnetic layers. At least one of the first and second magnetic layers has the following relationship between D (nm) and t (nm): D<0.9t+13, where D is a junction size corresponding to the length of a longest straight line on an end surface perpendicular to the thickness direction, and t is a layer thickness. The junction size is 30 nm or less.
    Type: Application
    Filed: October 20, 2014
    Publication date: August 11, 2016
    Applicant: TOHOKU UNIVERSITY
    Inventors: Shoji IKEDA, Hideo SATO, Shunsuke FUKAMI, Michihiko YAMANOUCHI, Fumihiro MATSUKURA, Hideo OHNO, Shinya ISHIKAWA
  • Patent number: 9406869
    Abstract: A semiconductor device includes: a first magnetic layer (1) disposed on a flat substrate surface; a second magnetic layer (3) disposed above the first magnetic layer (1) and magnetically coupled to the first magnetic layer (1) by magnetostatic coupling or exchange coupling; and a third thin film layer (8) formed between the first magnetic layer (1) and the second magnetic layer (3), the third thin film layer (8) having such a thickness as to avoid inhibiting the magnetic coupling between the first magnetic layer (1) and the second magnetic layer (3).
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: August 2, 2016
    Assignees: NEC CORPORATION, TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjou, Keizo Kinoshita, Hideo Ohno
  • Patent number: 9299435
    Abstract: Provided is a nonvolatile content addressable memory. Each word circuit includes a plurality of segments having an order relation. Each of the segments includes one or more memory cells. Each of the memory cells includes a nonvolatile storage element. Each of the segments includes a power switch for turning on/off a power of a memory cell of the segment. During stand-by, all the power switches are turned off, and, in search operation, the power switch is turned on as necessary for each of the segments.
    Type: Grant
    Filed: August 1, 2013
    Date of Patent: March 29, 2016
    Assignees: NEC CORPORATION, TOHOKU UNIVERSITY
    Inventors: Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Shoun Matsunaga, Takahiro Hanyu, Hideo Ohno
  • Patent number: 9202545
    Abstract: A magnetoresistance effect element including a recording layer of high thermal stability to perform perpendicular magnetic recording within a film surface, and a magnetic memory using the element. The element includes: a first ferromagnetic layer of an invariable magnetization direction; a second ferromagnetic layer of a variable magnetization direction; a first non-magnetic layer between the first and second ferromagnetic layers; current supply terminals connected to the first and second ferromagnetic layers; a non-magnetic coupling layer on a surface of the second ferromagnetic layer opposite the first non-magnetic layer; a third ferromagnetic layer of a variable magnetization direction on a surface of the non-magnetic coupling layer opposite the second ferromagnetic layer; and a second non-magnetic layer on a surface of the third ferromagnetic layer opposite the non-magnetic coupling layer.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: December 1, 2015
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hideo Sato, Shunsuke Fukami, Michihiko Yamanouchi, Shoji Ikeda, Fumihiro Matsukura, Hideo Ohno
  • Publication number: 20150332818
    Abstract: A magnetic material includes a structure in which a first magnetic layer 1 and a second magnetic layer 2 are stacked such that each layer is formed at least partially in a stacking direction by substantially one atomic layer. The first magnetic layer contains Co as a principal component. The second magnetic layer includes at least Ni. The magnetic material has magnetic anisotropy in the stacking direction. Preferably, an atomic arrangement within a film surface of the first magnetic layer and the second magnetic layer has six-fold symmetry.
    Type: Application
    Filed: November 11, 2013
    Publication date: November 19, 2015
    Inventors: Shunsuke FUKAMI, Hideo SATO, Michihiko YAMANOUCHI, Shoji IKEDA, Hideo OHNO
  • Patent number: 9153306
    Abstract: Provided is a tunnel magnetoresistive effect element such that a high TMR ratio and a low write current can be realized, and the thermal stability factor (E/kBT) of a recording layer and a pinned layer is increased while an increase in resistance of the element as a whole is suppressed, thus enabling a stable operation. On at least one of a recording layer 21 and a pinned layer 22 each comprising CoFeB, electrically conductive oxide layers 31 and 32 are disposed on a side opposite to a tunnel barrier layer 10.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: October 6, 2015
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hideo Ohno, Shoji Ikeda, Hiroyuki Yamamoto, Yosuke Kurosaki, Katsuya Miura
  • Patent number: 9135973
    Abstract: Provided are a magnetoresistance effect element with a stable magnetization direction perpendicular to film plane and a controlled magnetoresistance ratio, in which writing can be performed by magnetic domain wall motion, and a magnetic memory including the magnetoresistance effect element. The magnetoresistance ratio is controlled by forming a ferromagnetic layer of the magnetoresistance effect element from a ferromagnetic material including at least one type of 3d transition metal or a Heusler alloy. The magnetization direction is changed from a direction in the film plane to a direction perpendicular to the film plane by controlling the film thickness of the ferromagnetic layer on an atomic layer level.
    Type: Grant
    Filed: May 26, 2011
    Date of Patent: September 15, 2015
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hideo Ohno, Shoji Ikeda, Fumihiro Matsukura, Masaki Endoh, Shun Kanai, Katsuya Miura, Hiroyuki Yamamoto
  • Publication number: 20150248939
    Abstract: Provided is a magnetic domain wall displacement memory cell, including a recording layer including a magnetic film, the recording layer including: a magnetization reversal region in which magnetization is reversible; and first and second magnetization fixed regions that supply a spin-polarized electron to the magnetization reversal region. The magnetic domain wall displacement memory cell is configured so that a first region in which magnetization reversal occurs due to a first current flowing in a direction parallel to a film surface of the recording layer and a first magnetic field component in the direction parallel to the film surface of the recording layer is formed, and a second region in which no magnetization reversal occurs is formed.
    Type: Application
    Filed: September 13, 2013
    Publication date: September 3, 2015
    Applicants: NEC Corporation, Tohoku University
    Inventors: Ryusuke Nebashi, Noboru Sakimura, Tadahiko Sugibayashi, Yukihide Tsuji, Ayuka Tada, Hiroaki Honjou, Hideo Ohno
  • Publication number: 20150235703
    Abstract: Provided is a nonvolatile content addressable memory. Each word circuit includes a plurality of segments having an order relation. Each of the segments includes one or more memory cells. Each of the memory cells includes a nonvolatile storage element. Each of the segments includes a power switch for turning on/off a power of a memory cell of the segment. During stand-by, all the power switches are turned off, and, in search operation, the power switch is turned on as necessary for each of the segments.
    Type: Application
    Filed: August 1, 2013
    Publication date: August 20, 2015
    Applicants: TOHOKU UNIVERSITY, NEC CORPORATION
    Inventors: Noboru Sakimura, Ryusuke Nebashi, Tadahiko Sugibayashi, Shoun Matsunaga, Takahiro Hanyu, Hideo Ohno
  • Publication number: 20150200354
    Abstract: A semiconductor device includes: a first magnetic layer (1) disposed on a flat substrate surface; a second magnetic layer (3) disposed above the first magnetic layer (1) and magnetically coupled to the first magnetic layer (1) by magnetostatic coupling or exchange coupling; and a third thin film layer (8) formed between the first magnetic layer (1) and the second magnetic layer (3), the third thin film layer (8) having such a thickness as to avoid inhibiting the magnetic coupling between the first magnetic layer (1) and the second magnetic layer (3).
    Type: Application
    Filed: April 24, 2013
    Publication date: July 16, 2015
    Applicants: TOHOKU UNIVERSITY, NEC CORPORATION
    Inventors: Hiroaki Honjou, Keizo Kinoshita, Hideo Ohno
  • Patent number: 9070457
    Abstract: In magnetic tunnel junctions manufactured with use of a ferromagnetic material having perpendicular magnetic anisotropy, a difference in record retention time depending on stored information due to an imbalance in thermal stability between a parallel state and an anti-parallel state of magnetization, which correspond to bit information, is alleviated. A reference layer and a recording layer which constitute a magnetic tunnel junction are made different in area from each other so as to correct the difference in record retention time corresponding to stored information.
    Type: Grant
    Filed: May 24, 2012
    Date of Patent: June 30, 2015
    Assignee: Tohoku University
    Inventors: Hideo Ohno, Shoji Ikeda, Michihiko Yamanouchi, Hideo Sato, Katsuya Miura
  • Patent number: 9042165
    Abstract: A magnetoresistive effect element uses a perpendicularly magnetized material and has a high TMR ratio. Intermediate layers composed of an element metal having a melting point of 1600° C. or an alloy containing the metal on an outside of a structure consisting of a CoFeB layer, an MgO barrier layer, and a CoFeB layer. By inserting the intermediate layers, crystallization of the CoFeB layer during annealing is advanced from an MgO (001) crystal side, so that the CoFeB layer has a crystalline orientation in bcc (001).
    Type: Grant
    Filed: January 25, 2011
    Date of Patent: May 26, 2015
    Assignees: Hitachi, Ltd., Tohoku University
    Inventors: Shoji Ikeda, Hideo Ohno, Hiroyuki Yamamoto, Kenchi Ito, Hiromasa Takahashi
  • Publication number: 20150138877
    Abstract: A nonvolatile logic gate device is configured to include a resistive network of a memory structure in which at least three nonvolatile resistive elements are connected, a reference resistive network as a reference resistance providing a tolerance of the memory structure to a resistance value of the resistive network of the memory structure, a writing part operable to selectively write or rewrite a value of each of the nonvolatile resistive elements in the resistive network into a maximum or a minimum corresponding to a logical value to be read when data are stored into the resistive network, and a logic circuit structure operable to use, as a logical value of the memory structure, a value obtained by comparison between the resistance value of the resistive network and the resistance value of the reference resistive network.
    Type: Application
    Filed: May 15, 2013
    Publication date: May 21, 2015
    Applicants: TOHOKU UNIVERSITY, NEC CORPORATION
    Inventors: Ryusuke Nebashi, Noboru Sakimura, Yukihide Tsuji, Ayuka Tada, Tadahiko Sugibayashi, Takahiro Hanyu, Tetsuo Endoh, Hideo Ohno
  • Publication number: 20150109853
    Abstract: A magnetoresistance effect element including a recording layer of high thermal stability to perform perpendicular magnetic recording within a film surface, and a magnetic memory using the element. The element includes: a first ferromagnetic layer of an invariable magnetization direction; a second ferromagnetic layer of a variable magnetization direction; a first non-magnetic layer between the first and second ferromagnetic layers; current supply terminals connected to the first and second ferromagnetic layers; a non-magnetic coupling layer on a surface of the second ferromagnetic layer opposite the first non-magnetic layer; a third ferromagnetic layer of a variable magnetization direction on a surface of the non-magnetic coupling layer opposite the second ferromagnetic layer; and a second non-magnetic layer on a surface of the third ferromagnetic layer opposite the non-magnetic coupling layer.
    Type: Application
    Filed: March 25, 2013
    Publication date: April 23, 2015
    Applicant: TOHOKU UNIVERSITY
    Inventors: Hideo Sato, Shunsuke Fukami, Michihiko Yamanouchi, Shoji Ikeda, Fumihiro Matsukura, Hideo Ohno
  • Patent number: 8993351
    Abstract: [Object] To provide a method of manufacturing a perpendicular magnetization-type magnetic element, which does not need a step of depositing MgO. [Solving Means] The method of manufacturing a magnetoresistive element 1 according to the present invention includes laminating a first layer 30 on a base 10, the first layer 30 including a material containing at least one of Co, Ni, and Fe. Next, a second layer 40 is laminated on the first layer 30, the second layer 40 including Mg. Next, the Mg in the second layer 40 is oxidized to form MgO by applying an oxidation treatment to a laminated body including the first layer 30 and the second layer 40. Next, the second layer 40 is crystallized by applying a heat treatment to the laminated body, and the first layer 30 is caused to be perpendicularly magnetized. According to the manufacturing method, it is possible to manufacture a perpendicular magnetization-type CoFeB—MgO magnetic element without causing a problem arising from the deposition of MgO.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: March 31, 2015
    Assignees: Tohoku University, Ulvac, Inc.
    Inventors: Hiroki Yamamoto, Tadashi Morita, Hideo Ohno, Shoji Ikeda
  • Patent number: 8917541
    Abstract: Provided are a magneto resistive effect element with a stable magnetization direction perpendicular to a film plane and with a controlled magnetoresistance ratio, and a magnetic memory using the magneto resistive effect element. Ferromagnetic layers 106 and 107 of the magneto resistive effect element are formed from a ferromagnetic material containing at least one type of 3d transition metal such that the magnetoresistance ratio is controlled, and the film thickness of the ferromagnetic layers is controlled on an atomic layer level such that the magnetization direction is changed from a direction in the film plane to a direction perpendicular to the film plane.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: December 23, 2014
    Assignees: Hitachi, Ltd., Tohoku University
    Inventors: Hideo Ohno, Shoji Ikeda, Fumihiro Matsukura, Masaki Endoh, Shun Kanai, Hiroyuki Yamamoto, Katsuya Miura
  • Publication number: 20140355330
    Abstract: An integrated circuit that does not involve increase in power consumption or decrease in switching probability that occur when a latch circuit using STT-MTJ device, etc. of the prior art is operated at high speed is provided. The integrated circuit 1 includes: a memory element 1B where write occurs when a specified period ? has elapsed after a write signal is input; and a basic circuit element 1A, which is an elementary device constituting a circuit and has a data retaining function, and characterized in that an operation frequency f1 in a first operation mode in the process of information processing of the basic circuit element 1A satisfies the following relation: ?>?1/f1(0<?1?1).
    Type: Application
    Filed: December 4, 2012
    Publication date: December 4, 2014
    Applicant: TOHOKU UNIVERSITY
    Inventors: Tetsuo Endoh, Takashi Ohsawa, Hiroki Koike, Takahiro Hanyu, Hideo Ohno
  • Publication number: 20140340961
    Abstract: Provided is a tunnel magnetoresistive effect element such that a high TMR ratio and a low write current can be realized, and the thermal stability factor (E/kBT) of a recording layer and a pinned layer is increased while an increase in resistance of the element as a whole is suppressed, thus enabling a stable operation. On at least one of a recording layer 21 and a pinned layer 22 each comprising CoFeB, electrically conductive oxide layers 31 and 32 are disposed on a side opposite to a tunnel barrier layer 10.
    Type: Application
    Filed: November 8, 2011
    Publication date: November 20, 2014
    Applicants: HITACHI, LTD., TOHOKU UNIVERSITY
    Inventors: Hideo Ohno, Shoji Ikeda, Hiroyuki Yamamoto, Yosuke Kurosaki, Katsuya Miura
  • Patent number: 8837209
    Abstract: A relation between a drive current of a selection transistor of a magnetic memory and a threshold magnetization switching current of the magnetoresistance effect element is optimized. In order to optimize the relation between the drive current of the selection transistor and the threshold magnetization switching current of the magnetoresistance effect element 101 of the magnetic memory cell, a mechanism 601-604 for dropping the threshold magnetization switching current on “1” writing is provided that applies a magnetic field that is in the inverse direction of the pinned layer to the recording layer of the magnetoresistance effect element.
    Type: Grant
    Filed: February 17, 2011
    Date of Patent: September 16, 2014
    Assignees: Hitachi, Ltd., Tohoku University
    Inventors: Hideo Ohno, Shoji Ikeda, Katsuya Miura, Kazuo Ono, Riichiro Takemura, Hiromasa Takahashi