Patents by Inventor Hideo Sato

Hideo Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200090719
    Abstract: Provided is a magnetoresistance effect element in which the magnetization direction of the recording layer is perpendicular to the film surface and which has a high thermal stability factor ?, and a magnetic memory. A recording layer having a configuration of first magnetic layer/first non-magnetic coupling layer/first magnetic insertion layer/second non-magnetic coupling layer/second magnetic layer is sandwiched between the first and second non-magnetic layers and stacked so that a magnetic coupling force is generated between the first magnetic layer and the second magnetic layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: March 19, 2020
    Inventors: Koichi NISHIOKA, Tetsuo ENDOH, Shoji IKEDA, Hiroaki HONJO, Hideo SATO, Hideo OHNO
  • Patent number: 10586580
    Abstract: A magnetic tunnel junction element with a high tunnel magnetic resistance ratio can prevent a recording layer from being damaged. A reference layer includes a ferromagnetic body, and has magnetization direction fixed in the vertical direction. A barrier layer includes non-magnetic body, and disposed on one surface side of the reference layer. A recording layer is disposed to sandwich barrier layer between itself and reference layer. The recording layer includes a first ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in a vertical direction; a first non-magnetic layer including at least one of Mg, MgO, C, Li, Al, and Si, second non-magnetic layer including at least one of Ta, Hf, W, Mo, Nb, Zr, Y, Sc, Ti, V, and Cr, and second ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in a vertical direction.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: March 10, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Shoji Ikeda, Hideo Sato, Tetsuo Endoh, Hideo Ohno
  • Patent number: 10575766
    Abstract: [Object] To measure a form of light scattering in a body more simply. [Solution] A measurement device according to the present disclosure includes: a light source configured to emit at least one kind of measurement light belonging to a predetermined wavelength band toward a measurement region formed by at least a part of a living body; a detection unit configured such that a plurality of sensors are arranged regularly in a predetermined disposition and the measurement light emitted from the light source and transmitted through the living body is detected by the plurality of sensors; and an analysis unit configured to analyze at least one of rectilinearity of the measurement light in the living body and an optical distance from the light source using a detection result of the measurement light detected by the detection unit.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: March 3, 2020
    Assignee: Sony Corporation
    Inventor: Hideo Sato
  • Publication number: 20200044142
    Abstract: The present invention provides a magnetoresistance effect element which has a high thermal stability factor ? and in which a magnetization direction of a recording layer is a perpendicular direction with respect to a film surface, and a magnetic memory including the same. Magnetic layers of a recording layer of the magnetoresistance effect element are divided into at least two, and an Fe composition with respect to a sum total of atomic fractions of magnetic elements in each magnetic layer is changed before stacking the magnetic layers.
    Type: Application
    Filed: January 18, 2017
    Publication date: February 6, 2020
    Inventors: Hiroaki HONJO, Tetsuo ENDOH, Shoji IKEDA, Hideo SATO, Hideo OHNO
  • Patent number: 10542920
    Abstract: [Object] To more simply measure a scattering coefficient of an in-vivo component at any measurement location of a living body. [Solution] A measurement device according to the present disclosure includes: a light source configured to emit at least one kind of measurement light belonging to a predetermined wavelength band toward a measurement region formed by at least a part of a living body; a detection unit in which a plurality of sensors are arranged regularly in a predetermined disposition, the detection unit being provided on a same side as the light source with respect to the measurement region and configured to detect reflected light from the living body of the measurement light transmitted through a part of the living body with the plurality of sensors; and an analysis unit configured to analyze scattering characteristics of an in-vivo component present in the living body using a detection result of the reflected light detected by the detection unit.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: January 28, 2020
    Assignee: Sony Corporation
    Inventor: Hideo Sato
  • Patent number: 10488967
    Abstract: A shift register operates in a display period and a touch period in turn. The shift register circuit comprises a plurality of shift register units. Each shift register unit generates a pulse signal to a gate line, a following adjacent shift register unit, and an anterior adjacent shift register unit. Each shift register unit comprises a flip-flop (FF) circuit and an output circuit. The FF circuit controls potentials of an internal terminal and an internal inverted terminal based on a received a setting signal and a received reset signal. The output circuit generates the pulse signal related to a clock signal under a control of the internal terminal and the received internal inverted terminal. During the touch period, the potential of the internal terminal and the potential of the internal inverted terminal remain the same as the potential in the anterior display period.
    Type: Grant
    Filed: December 25, 2017
    Date of Patent: November 26, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Hideo Sato, Chi-Liang Wu
  • Patent number: 10477071
    Abstract: An image processing apparatus determines whether each of pixels in a scanned image is a color pixel or a monochrome pixel, determines whether each of blocks including the multiple pixels in the scanned image is a color block or a monochrome block, based on determination results of the respective pixels, and determines that the scanned image is a color image in a case where an arrangement pattern of blocks determined to be color blocks matches a predetermined pattern.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: November 12, 2019
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hideo Sato
  • Publication number: 20190304526
    Abstract: A magnetic tunnel junction element with a high MR ratio, and can prevent a recording layer from being damaged, and magnetic memory. A reference layer includes a ferromagnetic body, and has magnetization direction fixed in the vertical direction. A barrier layer includes non-magnetic body, and disposed on one surface side of the reference layer. A recording layer is disposed to sandwich barrier layer between itself and reference layer. The recording layer includes a first ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in vertical direction; a first non-magnetic layer including at least one of Mg, MgO, C, Li, Al, and Si, second non-magnetic layer including at least one of Ta, Hf, W, Mo, Nb, Zr, Y, Sc, Ti, V, and Cr, and second ferromagnetic layer including at least one of Co and Fe, and having a magnetization direction variable in vertical direction.
    Type: Application
    Filed: May 19, 2017
    Publication date: October 3, 2019
    Applicant: TOHOKU UNIVERSITY
    Inventors: Hiroaki HONJO, Shoji IKEDA, Hideo SATO, Tetsuo ENDOH, Hideo OHNO
  • Patent number: 10424725
    Abstract: A spintronics element including a ferromagnetic layer containing boron, and a diffusion stopper film covering a side face of the ferromagnetic layer partially or entirely, the side face in direct contact with diffusion stopper film, so as to prevent out-diffusion of the boron contained in the ferromagnetic layer. The diffusion stopper film contains boron at a concentration higher than a concentration of the boron in a portion of the ferromagnetic layer where the ferromagnetic layer contacts the diffusion stopper film.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: September 24, 2019
    Assignee: TOHOKU UNIVERSITY
    Inventors: Soshi Sato, Masaaki Niwa, Hiroaki Honjo, Shoji Ikeda, Hideo Sato, Hideo Ohno, Tetsuo Endoh
  • Patent number: 10395617
    Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: August 27, 2019
    Assignee: Japan Display Inc.
    Inventors: Hiroyuki Abe, Masahiro Maki, Hideo Sato, Hiroaki Komatsu
  • Publication number: 20190229262
    Abstract: A magnetic tunnel junction element configured by stacking, in a following stack order, a fixed layer formed of a ferromagnetic body and in which a magnetization direction is fixed, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body and in which the magnetization direction is fixed, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed by sandwiching an insertion layer formed of a nonmagnetic body between first and second ferromagnetic layers, wherein the magnetic coupling layer is formed using a sputtering gas in which a value of a ratio in which a mass number of an element used in the magnetic coupling layer divided by the mass number of the sputtering gas itself is 2.2 or smaller.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 25, 2019
    Applicant: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Shoji Ikeda, Hideo Sato, Tetsuo Endoh, Hideo Ohno
  • Publication number: 20190219633
    Abstract: A method and a system for measuring the thermal stability factor of a magnetic tunnel junction device, a semiconductor integrated circuit, and a production management method for the semiconductor integrated circuit, capable of measuring the thermal stability factors of individual devices in a relatively short period of time and quickly performing quality control during material development and at a production site. A meter measures change in resistance value of an evaluation MTJ for a predetermined period while causing a predetermined current to flow into the evaluation MTJ maintained at a predetermined temperature. An analyzer calculates a time constant in which a low-resistance state is maintained and a time constant in which a high-resistance state is maintained from the measured change in resistance value. A thermal stability factor of the evaluation MTJ is calculated on the basis of the calculated time constants and the predetermined current flowing into the evaluation MTJ.
    Type: Application
    Filed: March 22, 2017
    Publication date: July 18, 2019
    Applicant: TOHOKU UNIVERSITY
    Inventors: Kenchi ITO, Tetsuo ENDOH, Hideo SATO, Takashi SAITO, Masakazu MURAGUCHI, Hideo OHNO
  • Publication number: 20190198755
    Abstract: A method for producing a magnetic memory includes: forming a magnetic film having a non-magnetic layer between a first magnetic layer and a second magnetic layer on a substrate having an electrode layer; performing annealing treatment at a first treatment temperature in a state where a magnetic field is applied in a direction perpendicular to a film surface of the first or the second magnetic layer in vacuum; forming a magnetic tunnel junction element; forming a protective film protecting the magnetic tunnel junction element; a formation accompanied by thermal history, in which a constituent element of a magnetic memory is formed after the protective film formation on the substrate; and implementing annealing treatment at a second treatment temperature lower than the first treatment temperature on the substrate in an annealing treatment chamber, in vacuum or inert gas wherein no magnetic field is applied.
    Type: Application
    Filed: August 28, 2017
    Publication date: June 27, 2019
    Inventors: Kenchi ITO, Tetsuo ENDOH, Shoji IKEDA, Hideo SATO, Hideo OHNO, Sadahiko MIURA, Masaaki NIWA, Hiroaki HONJO
  • Patent number: 10329633
    Abstract: A high-strength seamless stainless steel pipe for oil country tubular goods that is excellent in terms of hot workability, sulfide stress cracking resistance, and corrosion resistance, and a method for manufacturing the steel pipe. The steel pipe has a chemical composition containing Cr and Ni so that the relationship Cr/Ni?5.3 is satisfied. A microstructure of the steel pipe includes mainly a tempered martensite phase. Additionally, a surface layer microstructure of the steel pipe includes a phase which looks white when subjected to etching with a Vilella etching solution, the phase having a thickness in the wall thickness direction from the outer surface of the pipe of 10 ?m or more and 100 ?m or less and dispersing in the outer surface of the pipe in an amount of 50% or more in terms of area fraction.
    Type: Grant
    Filed: May 20, 2015
    Date of Patent: June 25, 2019
    Assignee: JFE STEEL CORPORATION
    Inventors: Kazuki Fujimura, Yasuhide Ishiguro, Tetsu Nakahashi, Hideo Sato
  • Publication number: 20190189917
    Abstract: A magnetic tunnel junction element includes, in a following stack order, an underlayer formed of a metal material, a fixed layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, and a recording layer formed of a ferromagnetic body, or alternatively, the magnetic tunnel junction element includes, in a following stack order, a recording layer formed of a ferromagnetic body, a barrier layer formed of a nonmagnetic body, a reference layer formed of a ferromagnetic body, a magnetic coupling layer formed of a nonmagnetic body, an underlayer formed of a metal material, and a fixed layer formed of a ferromagnetic body, wherein the fixed layer is formed and stacked after performing plasma treatment to a surface of the underlayer having been formed.
    Type: Application
    Filed: March 21, 2017
    Publication date: June 20, 2019
    Applicant: TOHOKU UNIVERSITY
    Inventors: Hiroaki Honjo, Tetsuo Endoh, Shoji Ikeda, Hideo Sato, Hideo Ohno
  • Publication number: 20190122629
    Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: agate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Inventors: Hiroyuki ABE, Masahiro MAKI, Hideo SATO, Hiroaki KOMATSU
  • Patent number: 10263180
    Abstract: A magnetoresistance effect element includes a reference layer made of a ferromagnetic material, a recording layer made of a ferromagnetic material, and a barrier layer disposed between the reference layer and the recording layer. The reference layer and the recording layer have an in-plane magnetization direction parallel to a surface of the layers. The recording layer has a shape that has short axis and long axis perpendicular to the short axis in plan view. A first value obtained by dividing a thickness of the recording layer by a length of the short axis of the recording layer is greater than 0.3 and smaller than 1.
    Type: Grant
    Filed: July 22, 2017
    Date of Patent: April 16, 2019
    Assignee: TOHOKU UNIVERSITY
    Inventors: Hideo Sato, Shinya Ishikawa, Shunsuke Fukami, Shoji Ikeda, Fumihiro Matsukura, Hideo Ohno, Tetsuo Endoh
  • Publication number: 20190074433
    Abstract: A magnetoresistance effect element includes first and second magnetic layers having a perpendicular magnetization direction, and a first non-magnetic layer disposed adjacent to the first magnetic layer and on a side opposite to a side on which the second magnetic layer is disposed. An interfacial perpendicular magnetic anisotropy exists at an interface between the first magnetic layer and the first non-magnetic layer, and the anisotropy causes the first magnetic layer to have a magnetization direction perpendicular to the surface of the layers. An atomic fraction of all magnetic elements to all magnetic and non-magnetic elements included in the second magnetic layer is smaller than that of the first magnetic layer.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 7, 2019
    Applicant: TOHOKU UNIVERSITY
    Inventors: Hideo SATO, Shoji IKEDA, Mathias BERSWEILER, Hiroaki HONJO, Kyota WATANABE, Shunsuke FUKAMI, Fumihiro MATSUKURA, Kenchi ITO, Masaaki NIWA, Tetsuo ENDOH, Hideo OHNO
  • Publication number: 20190042721
    Abstract: A biometrics authentication system having a small and simple configuration and being capable of implementing both of biometrics authentication and position detection is provided. A biometrics authentication system includes: a light source emitting light to an object; a microlens array section condensing light from the object; a light-sensing device obtaining light detection data of the object on the basis of the light condensed by the microlens array section; a position detection section detecting the position of the object on the basis of the light detection data obtained in the light-sensing device; and an authentication section, in the case where the object is a living body, performing authentication of the living body on the basis of the light detection data obtained in the light-sensing device.
    Type: Application
    Filed: October 4, 2018
    Publication date: February 7, 2019
    Inventors: KENJI YAMAMOTO, HIDEO SATO, ISAO ICHIMURA, TOSHIO WATANABE, SHINICHI KAI, JUNJI KAJIHARA, KENGO HAYASAKA
  • Patent number: 10199004
    Abstract: A gate signal line driving circuit includes plural basic circuits, each outputting to a gate signal line a gate signal which is high during a high signal period and low during a low signal period. Each of the basic circuits includes: a gate line high voltage application circuit which is turned on in accordance with the high signal period to apply the high voltage to the gate signal line; a gate line low voltage application circuit which is turned on in accordance with the low signal period to apply the low voltage to the gate signal line; and a second gate line low voltage application circuit which is turned on to apply the low voltage to the gate signal line in at least a part of a period between turning off the gate line high voltage application circuit and turning on the gate line low voltage application circuit.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: February 5, 2019
    Assignee: Japan Display Inc.
    Inventors: Hiroyuki Abe, Masahiro Maki, Hideo Sato, Hiroaki Komatsu