Patents by Inventor Hideo Yamanaka

Hideo Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050202586
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Application
    Filed: April 13, 2005
    Publication date: September 15, 2005
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Publication number: 20050185282
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Application
    Filed: April 13, 2005
    Publication date: August 25, 2005
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Publication number: 20050180018
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Application
    Filed: April 13, 2005
    Publication date: August 18, 2005
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Publication number: 20050179048
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Application
    Filed: April 13, 2005
    Publication date: August 18, 2005
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Publication number: 20050173720
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Application
    Filed: April 13, 2005
    Publication date: August 11, 2005
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Patent number: 6894840
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Grant
    Filed: May 12, 2003
    Date of Patent: May 17, 2005
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Publication number: 20050074954
    Abstract: A method for producing an ultra-thin semiconductor chip and an ultra-thin back-illuminated solid-state image pickup device utilizing a semiconductor layer formed on a support substrate via an insulating layer to improve separation performance of a semiconductor layer from a support substrate and thereby improve the productivity and quality. The method uses two porous peeling layers on opposite sides of a substrate to produce an ultra-thin substrate.
    Type: Application
    Filed: October 7, 2003
    Publication date: April 7, 2005
    Inventor: Hideo Yamanaka
  • Publication number: 20050057705
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Application
    Filed: November 1, 2004
    Publication date: March 17, 2005
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Patent number: 6825070
    Abstract: A single crystal silicon is graphoepitaxially grown using a step formed on a substrate as a seed by a catalyst process, and the obtained single crystal silicon layer is used for a dual gate type MOSTFT in an electro-optical apparatus such as a display section of a peripheral driving circuit integration type LCD. A single crystal silicon thin film having high electron/hole mobility is formed into a uniform film at a relatively low temperature, which enables the manufacturing of an active matrix substrate incorporated with a high-performance driver which can be used in a TFT display.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: November 30, 2004
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuichi Satou, Hajime Yagi
  • Patent number: 6767755
    Abstract: A single-crystal silicon layer is formed by graphoepitaxy from a low-melting-point metal layer which contains dissolved polycrystalline or amorphous silicon, or from a melt of a silicon-containing low-melting-point metal, using step differences formed on a substrate as a seed for the epitaxial growth. This single-crystal silicon layer is used as dual-gate MOSTFTs, or bottom-gate MOSTFTs, of an electrooptical device such as an LCD integrating a display section and a peripheral-driving-circuit section. This process enables production of a uniform single-crystal silicon thin-film having high electron/hole mobility at a relatively low temperature. The display section includes LDD-nMOSTFTs or pMOSTFTs having high switching characteristics and a low leakage current. The peripheral-driving-circuit section includes cMOSTFTs, nMOSTFTs, pMOSTFTs, or a combination thereof, having high driving ability.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: July 27, 2004
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuuichi Sato, Hajime Yagi
  • Publication number: 20040134429
    Abstract: A reaction gas made of a hydrogen-based carrier gas and a silane gas or the like is brought in contact with a heated catalyzer of tungsten or the like, and a DC voltage not higher than a glow discharge starting voltage or a voltage produced by superimposing an AV voltage or an RF voltage on the DC voltage is applied on the produced reactive species, so as to provide kinetic energy and carry out vapor growth of a predetermined film on a substrate, thereby providing a film of high quality.
    Type: Application
    Filed: January 7, 2004
    Publication date: July 15, 2004
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Patent number: 6709512
    Abstract: When a polycrystalline or single crystal silicon layer is grown by catalytic CVD, a catalyst having a nitride covering at least its surface is used. In case that tungsten is used as the catalyst, tungsten nitride is formed as the nitride. The nitride is made by heating the surface of the catalyst to a high temperature around 1600 to 2100° C. in an atmosphere containing nitrogen prior to the growth. When the catalyst is heated to the temperature for its use or its nitrification, it is held in a hydrogen atmosphere.
    Type: Grant
    Filed: August 29, 2001
    Date of Patent: March 23, 2004
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka
  • Patent number: 6696309
    Abstract: An electrooptical device including a first substrate including a display section having pixel electrodes and a peripheral-driving-circuit section provided on a periphery of the display section, a second substrate, and an optical material disposed between the first substrate and the second substrate is produced as follows. A material layer having a high degree of lattice matching with single-crystal silicon is formed on one face of the first substrate. A polycrystalline or amorphous silicon layer is formed on the first substrate and then a low-melting-point metal layer is formed on or under the silicon layer on the first substrate, or a low-melting-point metal layer containing silicon is formed on the first substrate having the material layer. The silicon layer or the silicon is dissolved into the low-melting-point metal layer by a heat treatment.
    Type: Grant
    Filed: March 2, 2001
    Date of Patent: February 24, 2004
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuuichi Sato, Hajime Yagi
  • Publication number: 20040012734
    Abstract: A method of producing a microlens array includes a patterning step of forming a first optical resin layer having a first refractive index on a transparent substrate and forming a plurality of microlens planes arrayed in a two-dimensional pattern on the front surface of the first optical resin layer; a planarizing step of forming a planarized second optical resin layer; a joining step of providing a support layer on which a transparent protective film is previously formed; and a removing step of removing the support layer in such a manner that only the protective film remains on the second optical resin layer. The planarizing step is performed by filling irregularities of the microlens planes with a resin having a second refractive index and planarizing the front surface, opposed to the microlens planes, of the resin, to form the planarized second optical resin layer, and the joining step is performed by joining the support layer to the planarized second optical resin layer.
    Type: Application
    Filed: May 12, 2003
    Publication date: January 22, 2004
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Publication number: 20030226834
    Abstract: A laser annealer has a laser light source with at least one GaN-type semiconductor laser and is configured so as to form emission points that emit laser beams having a wavelength of 350 to 450 nm, and a scanning device for scanning an annealing surface with the laser beams. The laser annealer may have a spatial light modulator for modulating the laser beams, and in which pixel portions whose light modulating states change in accordance with control signals are arranged on a substrate. The invention is applied to a laser thin-film forming apparatus. The apparatus has a laser source that has at least one semiconductor laser and is configured so as to form emission points, and an optical system for focusing laser beams into a single beam in the width direction of a substrate.
    Type: Application
    Filed: June 9, 2003
    Publication date: December 11, 2003
    Applicant: FUJI PHOTO FILM CO., LTD. & FUJI PHOTO OPTICAL CO., LTD.
    Inventors: Hiromi Ishikawa, Akinori Harada, Kazuhiko Nagano, Yoji Okazaki, Takeshi Fujii, Hideo Yamanaka, Hiromitsu Yamakawa
  • Patent number: 6653212
    Abstract: A thin film forming apparatus S having a vacuum chamber 1, a substrate 10, a thermal catalyst 5, and a heating means 5a for heating this thermal catalyst 5, wherein a gas introduction system 3 for feeding the gas is connected in the vacuum chamber 1, the gas is fed from this gas introduction system 3 to the vacuum chamber 1, and thin films are formed on the surface of the substrate 10 by utilizing a thermal decomposition reaction or catalytic reaction by the thermal catalyst 5, the gas introduction system 3 is for introducing a carrier gas containing hydrogen and a material gas for forming the thin film on the substrate 10, and the carrier gas is constantly fed into the vacuum chamber 1 at least during the formation of the thin film.
    Type: Grant
    Filed: April 9, 2001
    Date of Patent: November 25, 2003
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto
  • Patent number: 6645835
    Abstract: A method for forming a semiconductor film capable allowing easy cleaning of the processing equipment and capable of forming an epitaxial film at low temperatures as well as a manufacturing method for semiconductor devices utilizing this forming method is needed for achieving selective crystalline growth on semiconductor film. The forming method comprises a process for forming a mask having an aperture exposing a substrate surface on substrate, and a process for forming a semiconductor film by selective crystalline growth on a semiconductor piece by means of catalytic chemical vapor deposition on a substrate surface exposed by an aperture on a mask; as well as a manufacturing method for semiconductor devices utilizing the semiconductor film forming method.
    Type: Grant
    Filed: March 16, 2000
    Date of Patent: November 11, 2003
    Assignee: Sony Corporation
    Inventors: Hisayoshi Yamoto, Hideo Yamanaka, Hajime Yagi, Yuuichi Sato
  • Publication number: 20030148565
    Abstract: The present invention provides a method capable of easily forming a polycrystalline or monocrystalline semiconductor thin film of polycrystalline silicon with a high degree of crystallization and high quality at low cost, and an apparatus for carrying out the method.
    Type: Application
    Filed: October 1, 2002
    Publication date: August 7, 2003
    Inventor: Hideo Yamanaka
  • Patent number: 6592771
    Abstract: A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polycrystalline silicon on the substrate is etched in vapor phase using reaction seeds or precursors thereof generated by contacting a reaction gas such as CF4 with a heated catalyst of for example tungsten.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: July 15, 2003
    Assignee: Sony Corporation
    Inventors: Hideo Yamanaka, Kikuo Kaise
  • Publication number: 20030124755
    Abstract: A single-crystal silicon layer is formed by graphoepitaxy from a low-melting-point metal layer which contains dissolved polycrystalline or amorphous silicon, or from a melt of a silicon-containing low-melting-point metal, using step differences formed on a substrate as a seed for the epitaxial growth. This single-crystal silicon layer is used as dual-gate MOSTFTs, or bottom-gate MOSTFTs, of an electrooptical device such as an LCD integrating a display section and a peripheral-driving-circuit section. This process enables production of a uniform single-crystal silicon thin-film having high electron/hole mobility at a relatively low temperature. The display section includes LDD-nMOSTFTs or pMOSTFTs having high switching characteristics and a low leakage current. The peripheral-driving-circuit section includes cMOSTFTs, nMOSTFTs, pMOSTFTs, or a combination thereof, having high driving ability.
    Type: Application
    Filed: November 20, 2002
    Publication date: July 3, 2003
    Inventors: Hideo Yamanaka, Hisayoshi Yamoto, Yuuichi Sato, Hajime Yagi