Patents by Inventor Hideo Yoshino

Hideo Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098291
    Abstract: A semiconductor device, including: a first semiconductor element formed at a first surface on a substrate, and has a first electrode portion formed thereon a first metal silicide film; a second semiconductor element formed at a second surface at a higher position than the first surface, and has a second electrode portion formed thereon a second metal silicide film and a hydrogen supply film configured to cover a part of an upper portion of the second metal silicide film; an interlayer insulating film formed on the first semiconductor element and the second semiconductor element; a first contact hole formed through the interlayer insulating film until the first metal silicide film; a second contact hole formed through the interlayer insulating film and the hydrogen supply film until the second metal silicide film; and a metal wiring embedded in each of the first contact hole and the second contact hole.
    Type: Application
    Filed: September 9, 2020
    Publication date: April 1, 2021
    Inventor: Hideo YOSHINO
  • Patent number: 10886267
    Abstract: The reference voltage generation device includes a constant current circuit which includes a first MOS transistor, and a voltage generation circuit which includes a second MOS transistor. The first MOS transistor includes a gate electrode, a source region, a drain region, and a channel impurity region which have a first conductivity type and has a first channel size. The second MOS transistor includes a gate electrode of a second conductivity type, and a source region, a drain region, and a channel impurity region which have the first conductivity type and has a second channel size different from the first channel size. The channel impurity regions have different impurity concentrations.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: January 5, 2021
    Assignee: ABLIC INC.
    Inventor: Hideo Yoshino
  • Patent number: 10695360
    Abstract: The present disclosure provides for the administration of ?-NMN, which increases the secretion of adiponectin. The present disclosure also provides an adiponectin secretion enhancer comprising ?-nicotinamide mononucleotide, a pharmaceutically acceptable salt thereof or a solvate thereof, and a dietary supplement containing the aforementioned secretion enhancer, which can be ingested in order to increase the secretion of adiponectin. Also disclosed are methods of treating insulin resistance-related diseases such as of metabolic syndrome, diabetes, hyperlipidemia, fatty liver disease, hypertension, obesity, and arteriosclerosis.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: June 30, 2020
    Assignee: Washington University
    Inventors: Jun Yoshino, Hisataka Yasuda, Hideo Arai, Tetsuro Enomoto
  • Publication number: 20190244956
    Abstract: The reference voltage generation device includes a constant current circuit which includes a first MOS transistor, and a voltage generation circuit which includes a second MOS transistor. The first MOS transistor includes a gate electrode, a source region, a drain region, and a channel impurity region which have a first conductivity type and has a first channel size. The second MOS transistor includes a gate electrode of a second conductivity type, and a source region, a drain region, and a channel impurity region which have the first conductivity type and has a second channel size different from the first channel size. The channel impurity regions have different impurity concentrations.
    Type: Application
    Filed: January 4, 2019
    Publication date: August 8, 2019
    Inventor: Hideo YOSHINO
  • Patent number: 10249713
    Abstract: A semiconductor device includes a MOS transistor and an ESD protection element comprised of an NMOS off transistor having a gate potential equal to a ground potential or a well potential. The off transistor has an N-type drain region and a P-type drain region in a drain active region thereof. The P-type region has a potential that is the potential of a P well or a P-type semiconductor substrate. A junction withstand voltage of a PN junction in the drain active region is the withstand voltage of the ESD protection element.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: April 2, 2019
    Assignee: ABLIC Inc.
    Inventor: Hideo Yoshino
  • Patent number: 10198023
    Abstract: A reference voltage generator is constructed to be equipped with a first constant current circuit which outputs a first constant current with respect to an input voltage, a second constant current circuit which outputs a second constant current, and a voltage generation circuit which generates a voltage based on an input current, and to take a current based on the first constant current and the second constant current as an input current of the voltage generation circuit and output a reference voltage from the voltage generation circuit.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: February 5, 2019
    Assignee: ABLIC INC.
    Inventors: Hideo Yoshino, Masahiro Hatakenaka
  • Publication number: 20180284833
    Abstract: A reference voltage generator is constructed to be equipped with a first constant current circuit which outputs a first constant current with respect to an input voltage, a second constant current circuit which outputs a second constant current, and a voltage generation circuit which generates a voltage based on an input current, and to take a current based on the first constant current and the second constant current as an input current of the voltage generation circuit and output a reference voltage from the voltage generation circuit.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 4, 2018
    Inventors: Hideo YOSHINO, Masahiro HATAKENAKA
  • Patent number: 9972625
    Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: May 15, 2018
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Keisuke Uemura, Hisashi Hasegawa, Shinjiro Kato, Hideo Yoshino
  • Publication number: 20170271321
    Abstract: A semiconductor device includes an off transistor using an NMOS as an ESD protection element that has N-type drain region (102), and P-type drain region (103) in a drain active region (105) . The P-type drain region (103) has a potential same as a potential of a P well or a P-type semiconductor substrate (106), and the ESD protection element has a withstand voltage that is a junction withstand voltage of a PN junction in the drain active region (105) .
    Type: Application
    Filed: March 13, 2017
    Publication date: September 21, 2017
    Inventor: Hideo YOSHINO
  • Publication number: 20170256545
    Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
    Type: Application
    Filed: May 18, 2017
    Publication date: September 7, 2017
    Inventors: Hirofumi HARADA, Keisuke UEMURA, Hisashi HASEGAWA, Shinjiro KATO, Hideo YOSHINO
  • Patent number: 9698147
    Abstract: A semiconductor integrated circuit device has a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate. The first N-channel type high withstanding-voltage transistor includes a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor includes a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors are capable of operating at 30 V or higher and are integrated on the N-type semiconductor substrate.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: July 4, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Hirofumi Harada, Keisuke Uemura, Hisashi Hasegawa, Shinjiro Kato, Hideo Yoshino
  • Patent number: 9552009
    Abstract: A reference voltage generator has a first N type depletion MOS transistor configured to cause a constant current to flow, and a second N type depletion MOS transistor diode-connected to the first N type depletion MOS transistor and configured to generate a reference voltage based on the constant current. The first and second N type depletion MOS transistors have the same temperature coefficient of a threshold voltage. The first N type depletion MOS transistor has a buried channel into which arsenic impurities are diffused. The second N type depletion MOS transistor has a buried channel into which phosphorous impurities are diffused.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: January 24, 2017
    Assignee: SII Semiconductor Corporation
    Inventors: Masayuki Hashitani, Hideo Yoshino
  • Publication number: 20160247804
    Abstract: Provided is a semiconductor integrated circuit device including a first N-channel type high withstanding-voltage MOS transistor and a second N-channel type high withstanding-voltage MOS transistor formed on an N-type semiconductor substrate, the first N-channel type high withstanding-voltage transistor including a third N-type low-concentration impurity region containing arsenic having a depth smaller than a P-type well region in a drain region within the P-type well region, and the second N-channel type high withstanding-voltage MOS transistor including a fourth N-type low-concentration impurity region that is adjacent to the P-type well region and has a bottom surface being in contact with the N-type semiconductor substrate. In this manner, the high withstanding-voltage NMOS transistors capable of operating at 30 V or higher are integrated on the N-type semiconductor substrate.
    Type: Application
    Filed: February 23, 2016
    Publication date: August 25, 2016
    Inventors: Hirofumi HARADA, Keisuke UEMURA, Hisashi HASEGAWA, Shinjiro KATO, Hideo YOSHINO
  • Patent number: 9213415
    Abstract: A reference voltage generator has a depletion mode MOS transistor of a first conductivity type for supplying a constant current flow, and an enhancement mode MOS transistor of the first conductivity type having a diode connection to the depletion mode MOS transistor for generating a reference voltage based on a constant current supplied by the depletion mode MOS transistor. The enhancement mode MOS transistor has a mobility substantially equal to a mobility of the depletion mode MOS transistor such that the enhancement mode MOS transistor and the depletion mode MOS transistor have substantially equal temperature characteristics.
    Type: Grant
    Filed: January 31, 2013
    Date of Patent: December 15, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Hideo Yoshino, Jun Osanai, Masayuki Hashitani, Yoshitsugu Hirose
  • Patent number: 9180813
    Abstract: A vehicle notification sound emitting apparatus is basically provided with a first sound emitting device, a second sound emitting device and a notification sound control device. The first sound emitting device emits a first intermittent notification sound inside a cabin interior of a vehicle. The second sound emitting device emits a second intermittent notification sound outside of the cabin interior of the vehicle. The notification sound control device operates the first and second sound emitting devices to separately emit the first and second intermittent notification sounds in at least a partially overlapping pattern in response to occurrence of a vehicle condition to convey a same type of vehicle information to both inside and outside of the cabin interior of the vehicle. The notification sound control device includes a cabin interior-exterior notification sound synchronizing section that is configured to synchronize the first and second intermittent notification sounds.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: November 10, 2015
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Hironori Saito, Katsumi Kimura, Tsuyoshi Kanuma, Hideo Yoshino, Yuji Watanabe, Toshiyuki Yamamoto
  • Patent number: 9041156
    Abstract: A reference voltage generating circuit has more than two first wells each having a first impurity concentration and more than two second wells each having a second impurity concentration different from the first impurity concentration. A first group of MOS transistors has more than two MOS transistors formed in respective ones of the first wells. A second group of MOS transistors has More than two MOS transistors formed in respective ones of the second wells.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: May 26, 2015
    Assignee: SEIKO INSTRUMENTS INC.
    Inventors: Hideo Yoshino, Hirofumi Harada, Jun Osanai
  • Publication number: 20150115930
    Abstract: Provided is a reference voltage generator having flat temperature characteristics. The reference voltage generator includes a depletion MOS transistor (5) of a first conductivity type connected so as to function as a current source and configured to cause a constant current to flow, and a depletion MOS transistor (6) of the first conductivity type that is diode-connected to the depletion MOS transistor (5), has the same buried channel and temperature characteristics as those of the depletion MOS transistor (5), and is configured to generate a reference voltage based on the constant current. The depletion MOS transistor (5) and the depletion MOS transistor (6) have the same temperature characteristics, and hence temperature characteristics of an output from the reference voltage generator become flat.
    Type: Application
    Filed: October 28, 2014
    Publication date: April 30, 2015
    Inventors: Masayuki HASHITANI, Hideo YOSHINO
  • Patent number: 8947159
    Abstract: Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits (10) is evaluated. Then only a unit reference voltage generation circuit (10) having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (10). Only fuses (13, 14) of the selected unit reference voltage generation circuit (10) are not cut, but other fuses (13, 14) are cut. Accordingly only the selected unit reference voltage generation circuit (10) operates, and the other unit reference voltage generation circuits (10) do not operate.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: February 3, 2015
    Assignee: Seiko Instruments Inc.
    Inventor: Hideo Yoshino
  • Publication number: 20140240038
    Abstract: Provided is a reference voltage generation circuit that has a flat temperature characteristic even when there are fluctuations in manufacturing step. After a semiconductor manufacturing process is finished, electrical characteristics of a semiconductor device are evaluated. Temperature characteristic of each reference voltage (VREF) of three unit reference voltage generation circuits (10) is evaluated. Then only a unit reference voltage generation circuit (10) having the most flat temperature characteristics is selected from among the three unit reference voltage generation circuits (10). Only fuses (13, 14) of the selected unit reference voltage generation circuit (10) are not cut, but other fuses (13, 14) are cut. Accordingly only the selected unit reference voltage generation circuit (10) operates, and the other unit reference voltage generation circuits (10) do not operate.
    Type: Application
    Filed: February 19, 2014
    Publication date: August 28, 2014
    Applicant: SEIKO INSTRUMENTS INC.
    Inventor: Hideo YOSHINO
  • Patent number: 8773253
    Abstract: A vehicle notification sound emitting apparatus is basically provided with a sound emitting device and a notification sound control device. The sound emitting device emits a movement notification sound to outside of a vehicle to inform a person in an area surrounding the vehicle that the vehicle is moving at a low speed. The notification sound control device operates the sound emitting device to selectively emit the movement notification sound. The notification sound control device includes a notification sound prohibiting section and a prohibition cancelling section. The notification sound prohibiting section prohibits an emission of the movement notification sound by the sound emitting device. The prohibition cancelling section cancels a notification sound emission prohibition imposed by the notification sound prohibiting section either upon a vehicle speed of the vehicle exceeding a prescribed vehicle speed or based on position information of the vehicle.
    Type: Grant
    Filed: February 7, 2011
    Date of Patent: July 8, 2014
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Hideo Yoshino, Tsuyoshi Kanuma, Yoshiro Tateishi, Hironori Saito, Katsumi Kimura