Patents by Inventor Hideo Yoshino

Hideo Yoshino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100025764
    Abstract: Provided is a manufacturing method for an offset MOS transistor capable of operating safely even under a voltage of 50 V or higher. In the offset MOS transistor which includes a LOCOS oxide film, the LOCOS oxide film formed in a periphery of a drain diffusion layer, in which a high withstanding voltage is required, is etched, and the drain diffusion layer is formed so as to spread into a surface region of a semiconductor substrate located below a region in which the LOCOS oxide film is thinned. As a result, end portions of the drain diffusion layer are covered by an offset diffusion layer, whereby electric field concentration occurring in a region of a lower portion of the drain diffusion layer can be relaxed.
    Type: Application
    Filed: July 28, 2009
    Publication date: February 4, 2010
    Inventors: Yuichiro Kitajima, Hideo Yoshino
  • Publication number: 20090283864
    Abstract: In order to reduce a device area, a bipolar transistor using temperature characteristics of a forward voltage generated between an emitter and a base has a structure in which a high concentration second conductivity type impurity region for a base electrode and a high concentration first conductivity type impurity region for a collector electrode are brought into direct contact with each other to prevent formation of an unnecessary isolation region. Further, an emitter region is disposed to self-align with a device isolation insulating film or a polycrystalline silicon arranged on a surface of a semiconductor substrate.
    Type: Application
    Filed: August 27, 2008
    Publication date: November 19, 2009
    Inventors: Hideo Yoshino, Hisashi Hasegawa
  • Publication number: 20080006879
    Abstract: Provided is a semiconductor integrated circuit device, which includes: a low-voltage MOS transistor having a source/drain region formed of a low impurity concentration region and a high impurity concentration region; and a high-voltage MOS transistor similarly having a source/drain region formed of a low impurity concentration region and a high impurity concentration region, in which, the source/drain high impurity concentration region of the low-voltage NMOS transistor is doped with arsenic, while the source/drain high impurity concentration region of the high-voltage NMOS transistor is doped with phosphorus.
    Type: Application
    Filed: June 26, 2007
    Publication date: January 10, 2008
    Inventors: Hirofumi Harada, Hisashi Hasegawa, Hideo Yoshino
  • Publication number: 20070210382
    Abstract: Provided is a semiconductor device formed to an SOI substrate including a MOS transistor in which a parasitic MOS transistor is suppressed. The semiconductor device formed on the SOI substrate by employing a LOCOS process is structured such that a part of a a polysilicon layer to becomes a gate electrode includes: a first conductivity type polysilicon region corresponding to a region of the silicon active layer which has a constant thickness and is to become a channel; and second conductivity type polysilicon regions corresponding to LOCOS isolation edges in each of which a thickness of the silicon active layer decreases.
    Type: Application
    Filed: February 7, 2007
    Publication date: September 13, 2007
    Inventors: Hideo Yoshino, Hisashi Hasegawa
  • Patent number: 5674771
    Abstract: A structure of a capacitor includes a first metal interconnection layer, a dielectric film, and a second metal interconnection layer. The dielectric film is formed on the first metal interconnection layer. The second metal interconnection layer is formed on the dielectric film. The dielectric film is a dielectric film formed by bias-ECR plasma CVD.
    Type: Grant
    Filed: March 22, 1993
    Date of Patent: October 7, 1997
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Katsuyuki Machida, Kazuo Imai, Hideo Yoshino, Yoshiharu Ozaki, Kenji Miura
  • Patent number: 4538167
    Abstract: The semiconductor device relates to a shorted junction type programmable read only memory semiconductor device. The memory consists of a semiconductor region including a PN junction or a Schottky junction and a control electrode coupled to the junction. The junction is destroyed or shorted by causing a field or carrier injection effect in the semiconductor region with a voltage impressed on the control electrode.
    Type: Grant
    Filed: September 8, 1981
    Date of Patent: August 27, 1985
    Assignee: Nippon Telegraph & Telephone Public Corporation
    Inventors: Hideo Yoshino, Eisuke Arai, Kazuhide Kiuchi