Patents by Inventor Hideto Ishiguro

Hideto Ishiguro has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010003447
    Abstract: A liquid crystal display device is obtained which performs point-sequential driving so that unevenness in brightness on a display screen becomes less noticeable. A signal line driving circuit that applies an image signal voltage sent from a signal processing circuit and a timing circuit to signal lines for performing point-sequential driving of the signal lines includes a driving direction switching circuit for inverting a driving direction of the point-sequential driving, and the signal processing circuit includes an image signal rearranging circuit for performing rearrangement of image signals, which is needed in accordance with inversion of the driving direction, in synchronization with the inversion of the driving direction.
    Type: Application
    Filed: December 4, 2000
    Publication date: June 14, 2001
    Inventors: Hiroyuki Murai, Hideto Ishiguro
  • Patent number: 6150283
    Abstract: To provide a TFT fabrication method capable of forming on a large-surface area substrate with uniform film thickness and at high deposition rate of film, while being a low-temperature process, a high-quality gate insulation film having good charge behavior by forming a silicon oxide film by a thin film transistor fabrication method having a channel region connected to a source region and a drain region, and a gate electrode confronting with the channel region through a gate insulation film, wherein in the formation process of said gate insulation film using plasma chemical vapor deposition under the condition that tetraethoxysilane is used as the feed gas to provide the silicon and the distance between electrodes for generating the plasma is about 15 mm or less.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: November 21, 2000
    Assignee: Seiko Epson Corporation
    Inventor: Hideto Ishiguro
  • Patent number: 6146928
    Abstract: A method for making a highly reliable non-single-crystal silicon thin film transistor, in which an underlying SiO.sub.2 film 15 is formed on a glass substrate 14 and then a polycrystalline silicon layer 17 is formed thereon. After patterning the polycrystalline silicon layer 17, a gate SiO.sub.2 film 18 is formed by an ECR-PECVD process or a TEOS-PECVD process. A gate electrode 19 is formed and source and drain regions 20, 20 are formed by an ion doping process. After forming a SiO.sub.2 insulating interlevel film 21 and providing a contact hole 22, an electrode 23 composed of an Al--Si--Cu film is formed. Finally, it is subjected to wet annealing at a temperature of 350.degree. C. for 3 hours.
    Type: Grant
    Filed: February 4, 1998
    Date of Patent: November 14, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Hideto Ishiguro, Takashi Nakazawa
  • Patent number: 5976989
    Abstract: To provide a TFT fabrication method capable of forming on a large-surface area substrate with uniform film thickness and at high deposition rate of film, while being a low-temperature process, a high-quality gate insulation film having good charge behavior by forming a silicon oxide film by a thin film transistor fabrication method having a channel region connected to a source region and a drain region, and a gate electrode confronting with the channel region through a gate insulation film, wherein in the formation process of said gate insulation film using plasma chemical vapor deposition under the condition that tetraethoxysilane is used as the feed gas to provide the silicon and the distance between electrodes for generating the plasma is about 15 mm or less.
    Type: Grant
    Filed: April 3, 1997
    Date of Patent: November 2, 1999
    Assignee: Seiko Epson Corporation
    Inventor: Hideto Ishiguro
  • Patent number: 5614730
    Abstract: There is disclosed an active matrix substrate including on a given substrate a thin film transistor, a scanning line connected to the gate of the thin film transistor, a data bus connected to the source of the thin film transistor, and a picture element electrode connected to the data bus through the thin film transistor, the active matrix substrate comprising a structure of the scanning line having the surface covered with an insulating film. A semiconductor layer covered with a gate insulating film constituting the thin film transistor, and a gate electrode constituting the thin film transistor, which are laid on each other in the stated order.
    Type: Grant
    Filed: November 8, 1991
    Date of Patent: March 25, 1997
    Assignee: Seiko Epson Corporation
    Inventors: Takashi Nakazawa, Hideto Ishiguro