Patents by Inventor Hideto Tamaso
Hideto Tamaso has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12100739Abstract: A method for producing a silicon carbide semiconductor device includes preparing a silicon carbide substrate, forming an insulating film on one main surface of the silicon carbide substrate, forming a contact hole in the insulating film and exposing the one main surface of the silicon carbide substrate at a bottom surface of the contact hole, forming an Si film on the bottom surface of the contact hole, forming an Ni film on the Si film, performing a first heat treatment at a first temperature at which Ni and Si react, after the forming of the Ni film, removing an unreacted portion of the Ni film that does not react with the Si film by wet etching after the first heat treatment, and performing a second heat treatment at a second temperature higher than the first temperature after the removing of the unreacted portion.Type: GrantFiled: July 14, 2020Date of Patent: September 24, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Hideto Tamaso
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Patent number: 12087821Abstract: A method for manufacturing a silicon carbide semiconductor device, includes the steps of depositing an insulating film on a principal surface of a silicon carbide substrate, forming a contact hole in the insulating film and exposing the principal surface, forming a Si film on bottom and a side surfaces of the contact hole, and a top surface of the insulating film, removing the Si film on the bottom surface of the contact hole and exposing the principal surface, depositing a Ni film on the bottom surface of the contact hole and the Si film, and performing a heat treatment to form a first alloy layer, which becomes an ohmic electrode, at the bottom surface of the contact hole by Si included in the substrate and the Ni film, and a second alloy layer at the top surface of the insulating film by the Si film and the Ni film.Type: GrantFiled: July 13, 2020Date of Patent: September 10, 2024Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.Inventor: Hideto Tamaso
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Publication number: 20220231129Abstract: A method for manufacturing a silicon carbide semiconductor device, includes the steps of preparing a silicon carbide substrate, depositing an insulating film on one principal surface of the silicon carbide substrate, forming a contact hole in the insulating film, and exposing the one principal surface at a bottom surface of the contact hole, forming a Si film on the bottom surface and a side surface of the contact hole, and a top surface of the insulating film, removing the Si film on the bottom surface of the contact hole, and exposing the one principal surface, depositing a Ni film on the bottom surface of the contact hole, and the Si film, and performing a heat treatment after depositing the Ni film, wherein the heat treatment forms a first alloy layer, which becomes an ohmic electrode, at the bottom surface of the contact hole by Si included in the silicon carbide substrate and the Ni film, and forms a second alloy layer at the top surface of the insulating film by the Si film and the Ni film.Type: ApplicationFiled: July 13, 2020Publication date: July 21, 2022Inventor: Hideto TAMASO
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Publication number: 20220208971Abstract: A method for producing a silicon carbide semiconductor device includes a step of preparing a silicon carbide substrate, a step of forming an insulating film on one main surface of the silicon carbide substrate, a step of forming a contact hole in the insulating film and exposing the one main surface of the silicon carbide substrate at a bottom surface of the contact hole, a step of forming an Si film on the bottom surface of the contact hole, a step of forming an Ni film on the Si film, a step of performing a first heat treatment at a first temperature at which Ni and Si react, after the step of forming the Ni film, a step of removing an unreacted portion of the Ni film that does not react with the Si film by wet etching after the first heat treatment, and a step of performing a second heat treatment at a second temperature higher than the first temperature after the step of removing the unreacted portion.Type: ApplicationFiled: July 14, 2020Publication date: June 30, 2022Inventor: Hideto TAMASO
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Patent number: 10453952Abstract: The second conductivity type thin film includes: a high-concentration layer having a first impurity concentration; a first electric field relaxing layer continuous to the high-concentration layer at an outer circumference of the high-concentration layer, the first electric field relaxing layer having a second impurity concentration lower than the first impurity concentration; a second electric field relaxing layer continuous to the first electric field relaxing layer at an outer circumference of the first electric field relaxing layer, the second electric field relaxing layer having a third impurity concentration lower than the second impurity concentration; and a first electric field diffusion layer continuous to the second electric field relaxing layer at an outer circumference of the second electric field relaxing layer, the first electric field diffusion layer having a fourth impurity concentration lower than the third impurity concentration.Type: GrantFiled: September 8, 2016Date of Patent: October 22, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiromu Shiomi, Hidenori Kitai, Hideto Tamaso, Kenji Fukuda
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Patent number: 10424642Abstract: The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.Type: GrantFiled: September 8, 2016Date of Patent: September 24, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hiromu Shiomi, Hidenori Kitai, Kenji Fukuda, Hideto Tamaso
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Patent number: 10381453Abstract: A method for manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide layer including an n-type region having an n conductivity type and a p-type region having a p conductivity type, forming a material layer containing titanium, aluminum, and silicon on the n-type region and the p-type region, and forming an electrode layer in contact with the n-type region and the p-type region by heating the material layer. In forming a material layer, composition of the material layer is determined such that a point (x, y, z) (x, y, and z each being a numeric value greater than 0) representing a composition ratio among titanium, aluminum, and silicon is included in a first triangular pyramidal region having four points of the origin (0, 0, 0), a point (1, 2, 2), a point (2, 1, 2) and a point (2, 2, 1) as vertices.Type: GrantFiled: September 7, 2015Date of Patent: August 13, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: So Tanaka, Shunsuke Yamada, Takahiro Matsui, Hideto Tamaso
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Publication number: 20190140056Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.Type: ApplicationFiled: December 17, 2018Publication date: May 9, 2019Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
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Patent number: 10192960Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.Type: GrantFiled: June 10, 2014Date of Patent: January 29, 2019Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
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Publication number: 20180331209Abstract: The current diffusion layer is interposed between the divided portions of the first base region. The second base region is provided adjacent to both sides of the trench current diffusion layer. The body region is provided on the trench current diffusion layer and the second base region. The source region is provided on the body region. The trench is provided to extend from a surface of the source region to the trench current diffusion layer through the source region and the body region. The trench has a bottom surface that is separated from and overlaps with the center portion of the first base region in a perpendicular direction. A width of the center portion in a horizontal direction is larger than a width of the bottom surface of the trench.Type: ApplicationFiled: September 8, 2016Publication date: November 15, 2018Applicant: Sumitomo Electric Industries, Ltd.Inventors: Hiromu Shiomi, Hidenori Kitai, Kenji Fukuda, Hideto Tamaso
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Publication number: 20180315813Abstract: The second conductivity type thin film includes: a high-concentration layer having a first impurity concentration; a first electric field relaxing layer continuous to the high-concentration layer at an outer circumference of the high-concentration layer, the first electric field relaxing layer having a second impurity concentration lower than the first impurity concentration; a second electric field relaxing layer continuous to the first electric field relaxing layer at an outer circumference of the first electric field relaxing layer, the second electric field relaxing layer having a third impurity concentration lower than the second impurity concentration; and a first electric field diffusion layer continuous to the second electric field relaxing layer at an outer circumference of the second electric field relaxing layer, the first electric field diffusion layer having a fourth impurity concentration lower than the third impurity concentration.Type: ApplicationFiled: September 8, 2016Publication date: November 1, 2018Inventors: Hiromu Shiomi, Hidenori Kitai, Hideto Tamaso, Kenji Fukuda
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Patent number: 10014376Abstract: A silicon carbide semiconductor device includes: a silicon carbide off substrate including a main surface having an off angle relative to a basal plane, the main surface being provided with a trench, the trench having a plurality of side walls and a bottom portion; a gate insulating film covering the side walls and the bottom portion; and a gate electrode provided on the gate insulating film, each of the side walls having an angle of more than 65° and not more than 80° relative to the basal plane in the trench, opening directions of the plurality of side walls being all at a silicon plane side or a carbon plane side.Type: GrantFiled: July 16, 2014Date of Patent: July 3, 2018Assignee: Sumitomo Electric Industries, Ltd.Inventors: Takeyoshi Masuda, Hideto Tamaso
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Publication number: 20170243948Abstract: A method for manufacturing a silicon carbide semiconductor device includes preparing a silicon carbide layer including an n-type region having an n conductivity type and a p-type region having a p conductivity type, forming a material layer containing titanium, aluminum, and silicon on the n-type region and the p-type region, and forming an electrode layer in contact with the n-type region and the p-type region by heating the material layer. In forming a material layer, composition of the material layer is determined such that a point (x, y, z) (x, y, and z each being a numeric value greater than 0) representing a composition ratio among titanium, aluminum, and silicon is included in a first triangular pyramidal region having four points of the origin (0, 0, 0), a point (1, 2, 2), a point (2, 1, 2) and a point (2, 2, 1) as vertices.Type: ApplicationFiled: September 7, 2015Publication date: August 24, 2017Inventors: So Tanaka, Shunsuke Yamada, Takahiro Matsui, Hideto Tamaso
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Patent number: 9620358Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer having a first main surface and a second main surface. A first recess including a side portion and a bottom portion is formed in the first main surface of the first silicon carbide layer. A second silicon carbide layer is formed in contact with the first main surface, the side portion, and the bottom portion. An image of a second recess formed at a position facing the first recess of the fourth main surface is obtained. Alignment is performed based on the image of the second recess. The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth of the first recess by a thickness of the second silicon carbide layer is more than 0.2.Type: GrantFiled: May 8, 2014Date of Patent: April 11, 2017Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hideto Tamaso
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Publication number: 20160204206Abstract: A silicon carbide semiconductor device includes: a silicon carbide off substrate including a main surface having an off angle relative to a basal plane, the main surface being provided with a trench, the trench having a plurality of side walls and a bottom portion; a gate insulating film covering the side walls and the bottom portion; and a gate electrode provided on the gate insulating film, each of the side walls having an angle of more than 65° and not more than 80° relative to the basal plane in the trench, opening directions of the plurality of side walls being all at a silicon plane side or a carbon plane side.Type: ApplicationFiled: July 16, 2014Publication date: July 14, 2016Applicant: Sumitomo Electric Industries, Ltd.Inventors: Takeyoshi Masuda, Hideto Tamaso
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Patent number: 9384981Abstract: A method of manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate, forming a first electrode on the silicon carbide substrate, establishing ohmic contact between the silicon carbide substrate and the first electrode by irradiating the first electrode with laser beams, and forming a second electrode on the first electrode. In the step of establishing ohmic contact, a surface of the first electrode is irradiated with laser beams such that arithmetic mean roughness of a surface of the second electrode is not greater than 0.2 ?m.Type: GrantFiled: July 8, 2015Date of Patent: July 5, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventors: Hideto Tamaso, Hiroyuki Kitabayashi, Keiji Wada
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Publication number: 20160181372Abstract: A silicon carbide layer includes a drift region, a body region and a source region. The drift region constitutes a first main surface and has a first conductivity type. The body region is provided on the drift region, and has a second conductivity type. It is provided on the body region to be separated from the drift region, constitutes a second main surface, and has the first conductivity type. The silicon carbide layer is provided with a trench including a first side wall portion and a first bottom portion. The silicon carbide layer is embedded in the drift region to face the first bottom portion, and includes a second conductivity type region having the second conductivity type. The second conductivity type region is electrically connected to the source region.Type: ApplicationFiled: June 10, 2014Publication date: June 23, 2016Inventors: Keiji Wada, Takeyoshi Masuda, Hideto Tamaso, Yu Saitoh, Toru Hiyoshi, Mitsuhiko Sakai
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Publication number: 20160118250Abstract: A method for manufacturing a silicon carbide semiconductor device includes the following steps. There is prepared a first silicon carbide layer having a first main surface and a second main surface. A first recess including a side portion and a bottom portion is formed in the first main surface of the first silicon carbide layer. A second silicon carbide layer is formed in contact with the first main surface, the side portion, and the bottom portion. An image of a second recess formed at a position facing the first recess of the fourth main surface is obtained. Alignment is performed based on the image of the second recess. The first main surface corresponds to a plane angled off relative to a {0001} plane. A ratio obtained by dividing a depth of the first recess by a thickness of the second silicon carbide layer is more than 0.2.Type: ApplicationFiled: May 8, 2014Publication date: April 28, 2016Inventor: Hideto TAMASO
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Publication number: 20160056041Abstract: A method of manufacturing a silicon carbide semiconductor device includes the steps of preparing a silicon carbide substrate, forming a first electrode on the silicon carbide substrate, establishing ohmic contact between the silicon carbide substrate and the first electrode by irradiating the first electrode with laser beams, and forming a second electrode on the first electrode. In the step of establishing ohmic contact, a surface of the first electrode is irradiated with laser beams such that arithmetic mean roughness of a surface of the second electrode is not greater than 0.2 ?m.Type: ApplicationFiled: July 8, 2015Publication date: February 25, 2016Inventors: Hideto TAMASO, Hiroyuki KITABAYASHI, Keiji WADA
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Patent number: 9263347Abstract: A silicon carbide substrate having a main surface angled off in an off direction relative to a {0001} plane is prepared. A protruding first alignment mark is formed on the main surface of the silicon carbide substrate. A second alignment mark is formed on the first alignment mark by forming a silicon carbide epitaxial layer on the first alignment mark. The first alignment mark includes a first region and a second region, the second region being in contact with the first region and extending from the first region in the off direction. The second alignment mark includes a first portion formed on the first region and a second portion formed on the second region. An alignment step includes the step of capturing an image of the first portion while not including the second portion, and recognizing an edge of the first portion based on the image.Type: GrantFiled: March 13, 2015Date of Patent: February 16, 2016Assignee: Sumitomo Electric Industries, Ltd.Inventor: Hideto Tamaso