Patents by Inventor Hidetomo Kobayashi

Hidetomo Kobayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240373709
    Abstract: An object is to provide a semiconductor device in which the number of control wirings is reduced. In a semiconductor device of one embodiment of the present invention, a first wiring (GLa) is connected to a first input terminal (54a) of a logic circuit (54) and a gate of a sixth transistor (M6); a second wiring (GLb) is connected to a second input terminal (54b) of the logic circuit (54), a gate of the third transistor (M3), a gate of the fourth transistor (M4), and a gate of the fifth transistor (M5); a gate of the first transistor (M1) is connected to an output terminal (54y) of the logic circuit (54); and the logic circuit (54) has a function of outputting a signal obtained by a logic operation of a signal input to the first input terminal (54a) and a signal input to the second input terminal (54b) to the output terminal (54y).
    Type: Application
    Filed: August 29, 2022
    Publication date: November 7, 2024
    Inventors: Yuki OKAMOTO, Tatsuya ONUKI, Hidetomo KOBAYASHI, Takanori MATSUZAKI, Munehiro KOZUMA
  • Patent number: 12120918
    Abstract: A display device with less display unevenness is provided. The display device includes a first layer and a second layer over the first layer; the first layer includes first circuits arranged in m rows and n columns; the second layer includes pixel blocks arranged in the m rows and the n columns; the pixel blocks each comprise pixels arranged in a rows and b columns; the pixel block includes a first wiring and a second wiring electrically connected to the pixel; the first wiring and the second wiring included in the pixel block in the i-th row and the j-th column are each electrically connected to the first circuit in the i-th row and the j-th column; the first wiring has a function of supplying an input signal from the first circuit to the pixel; and the second wiring has a function of supplying an output signal from the pixel to the first circuit.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: October 15, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidetomo Kobayashi, Takayuki Ikeda
  • Publication number: 20240331630
    Abstract: A novel electronic device is provided. The electronic device includes a display apparatus, an arithmetic portion, and a gaze detection portion, and the display apparatus includes a functional circuit and a display portion divided into a plurality of sub-display portions. The gaze detection portion has a function of detecting a user's gaze. The arithmetic portion has a function of dividing the plurality of sub-display portions between a first section and a second section using a detection result of the gaze detection portion. The first section includes a region overlapping with a user's gaze point. The functional circuit has a function of making a driving frequency of the second section lower than a driving frequency of the first section.
    Type: Application
    Filed: June 30, 2022
    Publication date: October 3, 2024
    Inventors: Munehiro KOZUMA, Tatsuya ONUKI, Hidetomo KOBAYASHI, Takanori MATSUZAKI, Yuki OKAMOTO, Minato ITO, Yusuke KOUMURA, Yoshiyuki KUROKAWA, Hisao IKEDA, Hiromichi GODO
  • Publication number: 20240331641
    Abstract: To provide a display apparatus with a novel structure. A display portion including a first subpixel, a second subpixel, a first gate line supplied with a first selection signal to scan the first subpixel, and a second gate line supplied with a second selection signal to scan the second subpixel; and a driver control circuit including a gate line driver circuit, a switching portion that allots the first selection signal or the second selection signal output from the gate line driver circuit to the first gate line or the second gate line to be output, and a timing control circuit that controls the switching portion are included.
    Type: Application
    Filed: July 28, 2022
    Publication date: October 3, 2024
    Inventors: Munehiro KOZUMA, Tatsuya ONUKI, Hidetomo KOBAYASHI
  • Publication number: 20240321205
    Abstract: The invention of the application is the invention regarding a semiconductor device and a method for driving the semiconductor device. The semiconductor device includes first and second transistors, first to fifth switches, first to third capacitors, and a display element.
    Type: Application
    Filed: June 23, 2022
    Publication date: September 26, 2024
    Inventors: Yuki OKAMOTO, Tatsuya ONUKI, Hidetomo KOBAYASHI, Munehiro KOZUMA, Takanori MATSUZAKI, Susumu KAWASHIMA, Yutaka OKAZAKI
  • Patent number: 12089459
    Abstract: A display apparatus with low power consumption and high image quality is provided. The display apparatus includes a light-emitting element, a first transistor, a second transistor, a third transistor, a first capacitor, and a second capacitor. Preferably, one electrode of the light-emitting element is electrically connected to one of a source and a drain of the first transistor; the one electrode of the light-emitting element is electrically connected to one electrode of the first capacitor; a gate of the first transistor is electrically connected to one of a source and a drain of the second transistor; the gate of the first transistor is electrically connected to one electrode of the second capacitor; the other electrode of the second capacitor is electrically connected to the other electrode of the first capacitor; and the other electrode of the second capacitor is electrically connected to one of a source and a drain of the third transistor.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: September 10, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidetomo Kobayashi, Hideaki Shishido, Takayuki Ikeda, Shuichi Katsui
  • Patent number: 12067802
    Abstract: A highly convenient imaging device is provided. Alternatively, a highly reliable imaging device is provided. Alternatively, a highly convenient authentication device is provided. Alternatively, a highly reliable authentication device is provided. The imaging device includes a substrate, a pixel array, and an adhesive layer. The substrate has flexibility, the pixel array is positioned over a first surface of the substrate, and the adhesive layer is positioned on a second surface facing the first surface of the substrate. The pixel array includes a light-receiving element and a light-emitting element. The light-receiving element has a function of sensing infrared light and includes a first pixel electrode, an active layer, and a common electrode. The light-emitting element has a function of emitting infrared light and includes a second pixel electrode, a light-emitting layer, and the common electrode. The active layer is positioned over the first pixel electrode and contains a first organic compound.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: August 20, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hidetomo Kobayashi, Takayuki Ikeda
  • Publication number: 20240265877
    Abstract: A display device that can be easily and more flexibly designed is provided. The display device includes a pixel circuit and a driver circuit in a display portion. The driver circuit includes a plurality of pulse output circuits. Each of the plurality of pulse output circuits has a function of driving a gate line. The pixel circuit is electrically connected to the gate line. Each of the plurality of pulse output circuits includes a first transistor. The pixel circuit includes a second transistor. A layer including the second transistor is over a layer including the first transistor, and the first transistor and the second transistor overlap with each other.
    Type: Application
    Filed: January 16, 2024
    Publication date: August 8, 2024
    Inventors: Hidetomo KOBAYASHI, Kouhei TOYOTAKA
  • Patent number: 12027091
    Abstract: A display device with a narrower frame can be provided. In the display device, a first layer, a second layer, and a third layer are provided to be stacked. The first layer includes a gate driver circuit and a data driver circuit, the second layer includes a demultiplexer circuit, and the third layer includes a display portion. In the display portion, pixels are arranged in a matrix, an input terminal of the demultiplexer circuit is electrically connected to the data driver circuit, and an output terminal of the demultiplexer circuit is electrically connected to some of the pixels. The gate driver circuit and the data driver circuit are provided to include a region overlapping some of the pixels. The gate driver circuit and the data driver circuit have a region where they are not strictly separated from each other and overlap each other. Five or more gate driver circuits and five or more data driver circuits can be provided.
    Type: Grant
    Filed: April 6, 2023
    Date of Patent: July 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takashi Nakagawa, Takayuki Ikeda, Hidetomo Kobayashi, Hideaki Shishido, Shuichi Katsui, Kiyotaka Kimura
  • Publication number: 20240215359
    Abstract: A display device with high display quality is provided. A highly reliable display device is provided. A display device with low power consumption is provided. A display device that can easily achieve higher definition is provided. A display device with both high display quality and high definition is provided. A display device with high contrast is provided. The display device includes a first wiring to a fourth wiring and a display portion including a first pixel to a third pixel. The second pixel is positioned between the first pixel and the third pixel in a plan view. Each pixel includes a first subpixel and a second subpixel. The first wiring has a function of applying a first potential to the second subpixel included in the first pixel. The second wiring has a function of applying the first potential to the first subpixel included in the second pixel. The third wiring has a function of applying the first potential to the second subpixel included in the second pixel.
    Type: Application
    Filed: March 20, 2022
    Publication date: June 27, 2024
    Inventors: Hajime KIMURA, Shuichi KATSUI, Hidetomo KOBAYASHI
  • Patent number: 12016236
    Abstract: Common noise is reduced from light-receiving data. A display module includes a display apparatus and a reading circuit. Each of a first pixel and a second pixel adjacent to each other in the display apparatus includes a light-receiving element and a light-emitting element. The reading circuit includes a differential input circuit. Common noise generated when display data is supplied to a light-emitting element, for example, may affect a first light-receiving signal output by the first pixel and a second light-receiving signal output by the second pixel. A first current is generated using the first light-receiving signal and a ramp signal, and a second current is generated using the second light-receiving signal and a first potential. The differential input circuit is controlled so that the first current and the second current have the same current value, whereby common noise can be removed from the first light-receiving signal.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: June 18, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Hidetomo Kobayashi
  • Publication number: 20240196650
    Abstract: A novel display apparatus is provided. The display apparatus includes a first wiring, a second wiring, a first transistor, and a plurality of second transistors. The first wiring extends in a first direction and is supplied with a gate signal. The second wiring extends in a second direction intersecting the first direction and is supplied with a source signal. A gate of the first transistor is electrically connected to the first wiring, one of a source and a drain of the first transistor is electrically connected to the second wiring, and the other of the source and the drain of the first transistor is electrically connected to each gate of the plurality of second transistors. The plurality of second transistors are connected in series or in parallel. The first transistor includes a first semiconductor layer in which current flows in the first direction or the second direction.
    Type: Application
    Filed: April 20, 2022
    Publication date: June 13, 2024
    Inventors: Hidetomo KOBAYASHI, Hideaki SHISHIDO, Shuichi KATSUI
  • Publication number: 20240196653
    Abstract: A novel display device is provided. The display device includes a first layer including a driver circuit, a second layer including a plurality of pixel circuits, and a third layer including a plurality of light-emitting elements; the second layer is provided over the first layer; the third layer is provided over the second layer; and a conductive layer is provided between the driver circuit and the plurality of pixel circuits. The driver circuit has a function of controlling operations of the plurality of pixel circuits. One of the plurality of pixel circuits is electrically connected to one of the plurality of light-emitting elements. The pixel circuit has a function of controlling emission luminance of the light-emitting element.
    Type: Application
    Filed: April 1, 2022
    Publication date: June 13, 2024
    Inventors: Yuki OKAMOTO, Susumu KAWASHIMA, Tatsuya ONUKI, Hidetomo KOBAYASHI, Munehiro KOZUMA, Takanori MATSUZAKI, Shunpei YAMAZAKI
  • Patent number: 11948515
    Abstract: A low-power display device is provided. The display device is provided with a plurality of display portions. A data driver circuit and an addition circuit are provided to have a region overlapping with the display portion. First analog data is output from the data driver circuit in the case where first digital data consisting of a first digital value is input to the data driver circuit, whereas second analog data is output from the data driver circuit in the case where second digital data consisting of a second digital value is input to the data driver circuit. The addition circuit generates analog data corresponding to digital data that has a high-order bit that is the first digital value and a low-order bit that is the second digital value, by adding the second analog data to the first analog data. An output terminal of the data driver circuit is directly connected to an input terminal of the addition circuit without through an amplifier circuit.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: April 2, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kouhei Toyotaka, Kiyotaka Kimura, Hidetomo Kobayashi, Kei Takahashi
  • Patent number: 11943554
    Abstract: An imaging device capable of executing image processing is provided. Analog data (image data) acquired through an imaging operation is retained in a pixel, and data obtained by multiplying the analog data by a given weight coefficient in the pixel can be extracted. The data is taken into a neural network or the like, whereby processing such as image recognition can be performed. Since an enormous amount of image data can be retained in pixels in an analog data state, processing can be performed efficiently.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: March 26, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Seiichi Yoneda, Yusuke Negoro, Hidetomo Kobayashi
  • Patent number: 11933974
    Abstract: An object is to provide an electronic device capable of recognizing a user's facial feature accurately. A glasses-type electronic device includes a first optical component, a second optical component, a frame, an imaging device, a feature extraction unit, and an emotion estimation unit. The frame is in contact with a side surface of the first optical component and a side surface of the second optical component. The imaging device is in contact with the frame and has a function of detecting part of a user's face. The feature extraction unit has a function of extracting a feature of the user's face from the detected part of the user's face. The emotion estimation unit has a function of estimating information on the user from the extracted feature.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Takayuki Ikeda, Hidetomo Kobayashi, Hideaki Shishido, Kiyotaka Kimura, Takashi Nakagawa, Kosei Nei, Kentaro Hayashi
  • Patent number: 11937007
    Abstract: An imaging device having a motion detecting function and an image processing function is provided. The imaging device can detect a difference between a reference frame image and a comparative frame image, and can switch from a motion detecting mode to a normal image capturing mode when a significant difference is detected. A low-frame-rate operation in the motion detecting mode can reduce power consumption. Moreover, the imaging device has an image recognition function in combination with the motion detecting function, so that switching from the motion detecting mode to the normal image capturing mode can be performed when a particular image is recognized.
    Type: Grant
    Filed: July 13, 2020
    Date of Patent: March 19, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Seiichi Yoneda, Yusuke Negoro, Takahiko Ishizu, Hidetomo Kobayashi
  • Publication number: 20240062724
    Abstract: A high-definition display device is provided. A small display device is provided. In the display device, a first layer and a second layer are stacked and provided. The first layer includes a gate driver circuit and a source driver circuit, and the second layer includes a display portion. The gate driver circuit and the source driver circuit are provided to include a region overlapping with the display portion. The gate driver circuit and the source driver circuit have an overlap region where they are not strictly separated from each other. Five or more gate driver circuits and five or more source driver circuits can be provided.
    Type: Application
    Filed: October 16, 2023
    Publication date: February 22, 2024
    Inventors: Takayuki IKEDA, Hidetomo KOBAYASHI, Hideaki SHISHIDO, Kiyotaka KIMURA, Takashi NAKAGAWA, Kosei NEI
  • Publication number: 20240063797
    Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.
    Type: Application
    Filed: August 31, 2023
    Publication date: February 22, 2024
    Inventors: Masashi FUJITA, Yutaka SHIONOIRI, Kiyoshi KATO, Hidetomo KOBAYASHI
  • Patent number: 11888446
    Abstract: A semiconductor device with a novel structure is provided. The semiconductor device includes a mixer circuit including a digital-analog converter circuit, a control circuit for controlling the digital-analog converter circuit, a power source control switch, and a plurality of Gilbert circuits. The plurality of Gilbert circuits each include an analog potential holding circuit for holding an analog potential output from the digital-analog converter circuit. The control circuit has a function of outputting a signal for controlling the analog potential holding circuit and the digital-analog converter circuit. The power source control switch has a function of stopping supply of a power source voltage to the control circuit in a period during which the analog potential held in the analog potential holding circuit is not updated. The analog potential holding circuit includes a first transistor. The first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: January 30, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kiyotaka Kimura, Takeya Hirose, Hidetomo Kobayashi, Takayuki Ikeda