Abstract: To provide a signal processing circuit including a nonvolatile memory circuit with a novel structure, the signal processing circuit includes an arithmetic portion, a memory, and a control portion for controlling the arithmetic portion and the memory. The control portion includes a set of a volatile memory circuit and a first nonvolatile memory circuit for storing data held in the volatile memory circuit, the memory includes a plurality of second nonvolatile memory circuits, and the first nonvolatile memory circuit and the second nonvolatile memory circuit each include a transistor having a channel in an oxide semiconductor layer and a capacitor in which one of a pair of electrodes is electrically connected to a node which is set in a floating state when the transistor is turned off.

Abstract: To provide a semiconductor device which can transmit/receive data to/from a reader/writer without interruption of operation by the reader/writer or the like. A semiconductor device capable of wireless communication includes an antenna circuit, a first demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% to 100%, both inclusive, a second demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% and 100%, both inclusive and from 10% and 30%, both inclusive and a logic circuit which selects one of a demodulation signal from the first circuit and a demodulation signal from the second circuit. When the antenna circuit receives an electromagnetic wave, the logic circuit selects the demodulation signal from the second circuit, and when the antenna circuit transmits an electromagnetic wave, the logic circuit selects the demodulation signal from the first circuit.

Abstract: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.

Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Abstract: A hierarchizing means 101 for blocking, of a first description which represents a functional circuit in an RTL, a second description and for converting the first description into a hierarchized third description; a first logic synthesis means 102 for logic synthesis of the third description; a first placement and routing means 103 for first placement and routing; a first substitution means 104 for substituting a fourth description indicating the unit circuit which is asynchronous for the second description; a second logic synthesis means 105 for logic synthesis of the fourth description; a second placement and routing means 106 for second placement and routing; a calculation means 107 for calculating a circuit on which the second placement and routing is performed; and a second substitution means 108 for substituting the circuit on which placement and routing is performed by the second placement and routing means 106 for a selected circuit on which placement and routing is performed by the first placement and

Abstract: A semiconductor device includes a memory portion, a logic portion, and a plurality of signal lines for electrically connecting the memory portion and the logic portion. In the case where a transfer rate between the semiconductor device and a communication device is ? [bps], a first clock frequency generated in the logic portion is K? [Hz] (K is an integer of 1 or more), the number of reading signal lines of the plurality of signal lines is n (n is an integer of 2 or more), and a second clock frequency generated in the logic portion is L?/n [Hz] (L is any integer satisfying L/n<K), data stored in the memory portion is read to the logic portion through the n reading signal lines with use of the second clock frequency L?/n [Hz].

Abstract: Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.

Abstract: Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.

Abstract: In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5x1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.

Abstract: A semiconductor device includes a memory portion, a logic portion, and a plurality of signal lines for electrically connecting the memory portion and the logic portion. In the case where a transfer rate between the semiconductor device and a communication device is ? [bps], a first clock frequency generated in the logic portion is K? [Hz] (K is an integer of 1 or more), the number of reading signal lines of the plurality of signal lines is n (n is an integer of 2 or more), and a second clock frequency generated in the logic portion is L?/n [Hz] (L is any integer satisfying L/n<K), data stored in the memory portion is read to the logic portion through the n reading signal lines with use of the second clock frequency L?/n [Hz].

Abstract: It is an object to prevent miswriting by radio in a relatively easy way in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication, in particular, in an RFID tag provided with an OTP memory or a write-once memory. Alternatively, it is an object to prevent data from being tampered. Further alternatively, it is an object to inhibit access to a memory in a relatively easy way and to inhibit reading of data in a semiconductor device which is capable of data communication (reception/transmission) through wireless communication. In a semiconductor device including a control circuit and an OTP memory, a memory includes at least a sector for preventing additional writing and an information sector.

Abstract: A demodulation signal is generated by provision of a demodulation signal generation circuit to the semiconductor device capable of wireless communication and by obtainment of a difference between voltages having opposite polarities by the demodulation signal generation circuit. Alternatively, a plurality of demodulation signal generation circuits and a selective circuit which selects a demodulation signal generation circuit depending on characteristics of a received signal are provided, where operation of a second demodulation signal generation circuit stops when a first demodulation signal generation circuit is operated. The selective circuit includes an inverter circuit, a flip-flop circuit, and a selector circuit. When the second demodulation signal generation circuit has a comparator and the like, power consumption thereof is reduced.

Abstract: The present invention provides a structure in which an amplitude-modulation mode and a frequency-modulation mode are switched.

Abstract: A hierarchizing means 101 for blocking, of a first description which represents a functional circuit in an RTL, a second description and for converting the first description into a hierarchized third description; a first logic synthesis means 102 for logic synthesis of the third description; a first placement and routing means 103 for first placement and routing; a first substitution means 104 for substituting a fourth description indicating the unit circuit which is asynchronous for the second description; a second logic synthesis means 105 for logic synthesis of the fourth description; a second placement and routing means 106 for second placement and routing; a calculation means 107 for calculating a circuit on which the second placement and routing is performed; and a second substitution means 108 for substituting the circuit on which placement and routing is performed by the second placement and routing means 106 for a selected circuit on which placement and routing is performed by the first placement and

Abstract: An object is to provide a semiconductor device having an antenna structure which is advantageous for miniaturization, without changing the number of steps and communication distance. One feature to achieve the above object is a semiconductor device including a substrate, a tag portion including a thin film element formed over the substrate, a first antenna, and a second antenna, in which the first antenna and the second antenna are formed in different layers separated by an insulating film, the first antenna and the second antenna are partially electrically connected to each other, the first antenna is formed of a same material and in a same layer as a source or drain wiring connected to the thin film element, and the second antenna is formed in a different layer from the source or drain wiring connected to the thin film element.

Abstract: To provide a semiconductor device which can transmit/receive data to/from a reader/writer without interruption of operation by the reader/writer or the like. A semiconductor device capable of wireless communication includes an antenna circuit, a first demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% to 100%, both inclusive, a second demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% and 100%, both inclusive and from 10% and 30%, both inclusive and a logic circuit which selects one of a demodulation signal from the first circuit and a demodulation signal from the second circuit. When the antenna circuit receives an electromagnetic wave, the logic circuit selects the demodulation signal from the second circuit, and when the antenna circuit transmits an electromagnetic wave, the logic circuit selects the demodulation signal from the first circuit.

Abstract: Initialization of a semiconductor device can be efficiently performed, which transmits and receives data through wireless communication. The semiconductor device includes an antenna, a power source circuit, a circuit which uses a DC voltage generated by the power source circuit as a power source voltage, and a resistor. The antenna includes a pair of terminals and receives a wireless signal (a modulated carrier wave). The power source circuit includes a first terminal and a second terminal and generates a DC voltage between the first terminal and the second terminal by using a received wireless signal (the modulated carrier wave). The resistor is connected between the first terminal and the second terminal. In this manner, the semiconductor device and the wireless communication system can transmit and receive data accurately.

Abstract: A demodulation signal is generated by provision of a demodulation signal generation circuit to the semiconductor device capable of wireless communication and by obtainment of a difference between voltages having opposite polarities by the demodulation signal generation circuit. Alternatively, a plurality of demodulation signal generation circuits and a selective circuit which selects a demodulation signal generation circuit depending on characteristics of a received signal are provided, where operation of a second demodulation signal generation circuit stops when a first demodulation signal generation circuit is operated. The selective circuit includes an inverter circuit, a flip-flop circuit, and a selector circuit. When the second demodulation signal generation circuit has a comparator and the like, power consumption thereof is reduced.

Abstract: The present invention is an article management system using a central management device with an interrogator and an alarm portion. Because the central management device and a central response device worn by a user of the system are provided separately, loss of the central management device can be prevented. The central response device is worn by a user. The central response device communicates with the central management device wirelessly and includes a detector that detects when the communication distance reaches or exceeds a given value and an alarm portion that notifies the user of this. The central management device communicates wirelessly with one or more articles in which a response device is installed.

Abstract: The present invention provides a structure in which an amplitude-modulation mode and a frequency-modulation mode are switched.