Abstract: A signal processing circuit includes a memory and a control portion configured to control the memory. The control portion includes a volatile memory circuit including data latch terminals, a first non-volatile memory circuit electrically connected to one of the data latch terminals, a second non-volatile memory circuit electrically connected to the other of the data latch terminals, and a precharge circuit having a function of supplying a potential that is a half of a high power supply potential to the one and the other of the data latch terminals. Each of the first non-volatile memory circuit and the second non-volatile memory circuit includes a transistor having a channel formation region including an oxide semiconductor and a capacitor connected to a node that is brought into a floating state by turning off the transistor.

Abstract: A source line through which a video signal is transmitted also serves as a driving electrode of a touch sensor. To perform display, a video signal is transmitted to the source line. To sense the touch, a driving signal is transmitted to the source line. A circuit for transmitting the video signal and the driving signal to the source line has a structure in which a period for transmitting the driving signal is added in the wiring through which the digital video signal is transmitted and the output to the source line is switched by using a switching circuit. Alternatively, the circuit has a structure in which a period for transmitting the driving signal is added in a wiring through which a latch signal is transmitted and the output to the source line is switched.

Abstract: A semiconductor device in which an increase in the degree of wiring congestion due to an increase in the number of output terminals of a driver IC can be reduced is provided. In a shift register of the driver IC, pulse signals are sequentially output in different directions. For example, pulse signal output circuits are provided so as to sequentially output pulse signals in ascending order from right to left and then sequentially output pulse signals in ascending order from left to right. With such a structure, output signals of the driver IC can be output not only from a side opposite to a side along which an input terminal is provided, but also from a side along which the input terminal is provided; thus, the number of output terminals can be increased without an increase in the degree of wiring congestion.

Abstract: A first field-effect transistor provided over a substrate in which an insulating region is provided over a first semiconductor region and a second semiconductor region is provided over the insulating region; an insulating layer provided over the substrate; a second field-effect transistor that is provided one flat surface of the insulating layer and includes an oxide semiconductor layer; and a control terminal are provided. The control terminal is formed in the same step as a source and a drain of the second field-effect transistor, and a voltage for controlling a threshold voltage of the first field-effect transistor is supplied to the control terminal.

Abstract: A command sequence is restarted from the middle even when supply of power supply voltage to an internal circuit in a wireless tag is temporarily stopped (a power flicker occurs). A register or a cache memory included in a signal processing circuit in the wireless tag continues to retain data even after the supply of power supply voltage is stopped. After the power flicker occurs, the signal processing circuit in the wireless tag is returned to the state before the supply of power supply voltage is stopped and can restart signal processing. Consequently, the command sequence can be restarted from the middle.

Abstract: A microcontroller which operates in a low power consumption mode is provided. A microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register in the peripheral circuit is provided in an interface with a bus line. A power gate for controlling supply control is provided. The microcontroller can operate not only in a normal operation mode where all circuits are active, but also in a low power consumption mode where some of the circuits are active. A volatile memory and nonvolatile memory are provided in a register, such as a register of the CPU. Data in the volatile memory is backed up in the nonvolatile memory before the power supply is stopped. In the case where the operation mode returns to the normal mode, when power supply is started again, data in the nonvolatile memory is written back into the volatile memory.

Abstract: A semiconductor device with short overhead time. The semiconductor device includes a first wiring supplied with a power supply potential, a second wiring, a switch for controlling electrical connection between the first wiring and the second wiring, a load electrically connected to the second wiring, a transistor whose source and drain are electrically connected to the second wiring, and a power management unit having functions of controlling the conduction state of the switch and controlling a gate potential of the transistor. A channel formation region of the transistor is included in an oxide semiconductor film.

Abstract: A dynamic logic circuit in which the number of elements is reduced, the layout area is reduced, the power loss is reduced, and the power consumption is reduced is provided. A semiconductor device including a dynamic logic circuit includes a first transistor in which a channel is formed in silicon and a second transistor in which a channel is formed in an oxide semiconductor. Here, a structure in which the second transistor is provided over the first transistor can be employed. A structure in which an insulating film is provided over the first transistor, and the second transistor is provided over the insulating film can be employed. A structure in which a top surface of the insulating film is planarized can be employed. A structure in which the second transistor has a region overlapping with the first transistor can be employed.

Abstract: To provide a microcontroller that can operate in a low power consumption mode. The microcontroller includes a CPU, a memory, and a peripheral circuit such as a timer circuit. A register of the peripheral circuit is formed at an interface with a bus line. A power gate is provided for control of power supply, and the microcontroller can operate in the low power consumption mode where some circuits alone are active, in addition to in a normal operation mode where all circuits are active. A register with no power supply in the low power consumption mode, such as a register of the CPU, includes a volatile memory and a nonvolatile memory.

Abstract: A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node.

Abstract: A semiconductor device in which the power consumption of a register is low is provided. Further, a processing unit whose operation speed is high and whose power consumption is low is provided. In the semiconductor device, a register operating at high speed and a nonvolatile FILO (first-in-last-out) register capable of reading and writing data from/to the register are provided.

Abstract: A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit through the selection circuit. The data line is electrically connected to the flip-flop circuit. The bit line is electrically connected to the nonvolatile memory circuit through the selection circuit. The selection circuit selectively stores data based on a potential of the data line or a potential of the bit line in the nonvolatile memory circuit.

Abstract: The data in a volatile memory may conventionally be lost even in case of a very short time power down or supply voltage drop such as an outage or sag. In view of the foregoing, an object is to extend data retention time even with a volatile memory for high-speed data processing. Data retention time can be extended by backing up the data content stored in the volatile memory in a memory including a capacitor and an oxide semiconductor transistor.

Abstract: A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract: A semiconductor device including a test circuit is miniaturized. The semiconductor device includes r first input terminals (r is an integer of 2 or more), a second input terminal, r functional circuits, a demultiplexer, and a switch circuit. The demultiplexer is a pass transistor logic circuit. R output terminals of the demultiplexer are electrically connected to respective input terminals of the functional circuit and the input terminal is electrically connected to the second input teiminal. Input terminals of the r circuits are electrically connected to the respective first input terminals through the switch circuit. For example, a signal for verification is input to the first input terminal in verification of the functional circuit to operate the demultiplexer. One signal for verification is input to r functional circuits by the demultiplexer.

Abstract: A current measurement method with which an extremely low current can be measured is provided. In the method, a charge written to a first terminal of a capacitor through a transistor under test is retained, data on the correspondence between a potential V of the first terminal of the capacitor and Time t is generated, and a stretched exponential function represented by Formula (a1) is fitted to the data to determine parameters of Formula (a1). The derivative of Formula (a1) with respect to time gives a stretched exponential function describing an off-state current of the transistor under test. The potential of the first terminal of the capacitor is measured using an on-state current of a transistor whose gate is connected to the first terminal of the capacitor.

Abstract: A semiconductor device capable of retaining data for a long time is provided. The semiconductor device includes first to third transistors, a fourth transistor including first and second gates, first to third nodes, a capacitor, and an input terminal. A source of the first transistor is connected to the input terminal. A drain of the first transistor and a source of the second transistor are connected to the first node. A gate of the second transistor, a drain of the second transistor, and a source of the third transistor are connected to the second node. A gate of the third transistor, a drain of the third transistor, the capacitor, and the second gate of the fourth transistor are connected to the third node.

Abstract: The circuit includes a first wiring for supplying a power supply potential to a signal processing circuit, a transistor for controlling electrical connection between the first wiring and a second wiring for supplying the a power supply potential, and a transistor for determining whether or not the first wiring is grounded. At least one of the two transistors is a transistor whose channel is formed in the oxide semiconductor layer. This makes it possible to reduce power consumption due to cutoff current of at least one of the two transistors.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.