Patents by Inventor Hidetoshi Fujimoto

Hidetoshi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170322598
    Abstract: A display device (10) includes a foldable case unit (100) and a flexible display panel (200). The case unit (100) includes an elongated connecting plate (130), and a lower case (110) and an upper case (120) coupled to the connecting plate (130) via hinge parts (141 and 142), respectively. The upper case (120) has a variable dimension in a y direction. In the opened case unit (100), the lower case (110), the connecting plate (130), and the upper case (120) are aligned flush with one another in the y direction. In the folded case unit (100), the dimension of the upper case (120) in the y direction is larger than the dimension in the opened case unit (100), and the display panel (200) is accommodated in a space surrounded with the lower case (110), the connecting plate (130), and the upper case (120).
    Type: Application
    Filed: November 10, 2015
    Publication date: November 9, 2017
    Inventor: Hidetoshi FUJIMOTO
  • Patent number: 9412825
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida, Yukako Murakami, Takako Motai
  • Patent number: 9412856
    Abstract: A semiconductor device includes a first and second nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger the first nitride semiconductor layer. Source and drain electrodes are formed spaced from each other on the second nitride semiconductor layer. A third nitride semiconductor layer is formed on the second nitride semiconductor layer between the source and drain electrodes. A gate electrode is formed on the third nitride semiconductor layer. The third nitride semiconductor layer comprises at least two first layers and at least one a second layer which has a lower p-type dopant concentration than the first layer. The second layer also has a band gap larger than the first layer. The lowermost layer and the uppermost layer in the third nitride semiconductor layer stack are the first layers.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Fujimoto
  • Patent number: 9412857
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: August 9, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito, Toru Sugiyama
  • Publication number: 20160079410
    Abstract: A semiconductor device includes a first electrode, a second electrode, a third electrode, and a nitride semiconductor layer. The first electrode has a first surface. The second electrode has a second surface. The second surface is provided with a plurality of convex portions and concave portions. The second electrode is spaced from the first electrode in a first direction. The third electrode is spaced from the first electrode in a second direction intersecting the first direction. The nitride semiconductor layer is provided between the first surface and the second surface, and between the third electrode and the second surface.
    Type: Application
    Filed: March 3, 2015
    Publication date: March 17, 2016
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI
  • Patent number: 9165922
    Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: October 20, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Takeshi Uchihara, Naoko Yanase, Toshiyuki Naka, Tetsuya Ohno, Tasuku Ono
  • Publication number: 20150263001
    Abstract: A semiconductor device includes a first semiconductor layer and a second semiconductor layer formed on the first semiconductor layer. A first control electrode is on the first semiconductor layer with a first insulating layer between the first control electrode and the first semiconductor layer. A second control electrode is on the first semiconductor layer with a second insulating layer between the second control electrode and the first semiconductor layer, a distance between the first control electrode and the first semiconductor layer is less than a distance between the second control electrode. A wiring electrically connects the first control electrode and the second control electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Yasunobu SAITO, Hidetoshi FUJIMOTO, Akira YOSHIOKA, Takeshi UCHIHARA, Toshiyuki NAKA, Tasuku ONO
  • Publication number: 20150263630
    Abstract: In one embodiment, a power supply circuit includes a first circuit including one or more first switching devices, and a first controller configured to control the first switching devices, the first circuit being configured to output a first voltage. The power supply circuit further includes a second circuit including one or more second switching devices which include a normally-on device, and a second controller configured to control the second switching devices, the second circuit being configured to output a second voltage generated from the first voltage. The second controller transmits a first signal for allowing the first circuit to output the first voltage, based on a value of a voltage or a current at a first node in the second circuit. The first controller allows the first circuit to output the first voltage by controlling the first switching devices in accordance with the first signal.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Toshiyuki Naka, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Publication number: 20150263700
    Abstract: According to one embodiment, a semiconductor device includes a GaN-based semiconductor layer, a resonator that uses a first portion of the GaN-based semiconductor layer as a piezoelectric layer to resonate, and a transistor that uses a second portion of the GaN-based semiconductor layer as a channel layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Yoshikazu SUZUKI
  • Publication number: 20150263155
    Abstract: A semiconductor device includes a first nitride semiconductor layer and a second nitride semiconductor layer having a band gap wider than the first nitride semiconductor layer. Source and drain electrodes are provided on the second nitride semiconductor layer. A third nitride semiconductor layer is provided between the source electrode and the drain electrode on the second nitride semiconductor layer. The third nitride semiconductor layer has an impurity concentration of 1×1017 atoms/cm3 or less, and a band gap narrower than the second nitride semiconductor layer. A p-type fourth nitride semiconductor layer is provided on the third nitride semiconductor layer, and a gate electrode is provided on the fourth nitride semiconductor layer.
    Type: Application
    Filed: September 2, 2014
    Publication date: September 17, 2015
    Inventor: Hidetoshi FUJIMOTO
  • Publication number: 20150263157
    Abstract: A semiconductor device of an embodiment includes: an n-type nitride semiconductor layer; an insulating layer selectively provided on the nitride semiconductor layer; an n-type first nitride semiconductor region provided on the nitride semiconductor layer and the insulating layer; an n-type second nitride semiconductor region provided on the insulating layer; a p-type third nitride semiconductor region provided between the first nitride semiconductor region and the second nitride semiconductor region; a gate insulating film provided on the third nitride semiconductor region; a gate electrode provided on the gate insulating film; a first electrode electrically connected to the second nitride semiconductor region; and a second electrode that is provided on the opposite side of the nitride semiconductor layer from the insulating layer, and is electrically connected to the nitride semiconductor layer.
    Type: Application
    Filed: September 17, 2014
    Publication date: September 17, 2015
    Inventor: Hidetoshi Fujimoto
  • Publication number: 20150263152
    Abstract: A semiconductor device includes a GaN-based semiconductor layer, a source electrode on the GaN-based semiconductor layer, a drain electrode on the GaN-based semiconductor layer, and a gate electrode formed on the GaN-based semiconductor layer between the source electrode and the drain electrode. A first layer is in contact with the GaN-based semiconductor layer between the gate electrode and the drain electrode.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventors: Takaaki YASUMOTO, Naoko YANASE, Kazuhide ABE, Takeshi UCHIHARA, Yasunobu SAITO, Toshiyuki NAKA, Akira YOSHIOKA, Tasuku ONO, Tetsuya OHNO, Hidetoshi FUJIMOTO, Shingo MASUKO, Masaru FURUKAWA, Yasunari YAGI, Miki YUMOTO, Atsuko IIDA, Yukako MURAKAMI, Takako MOTAI
  • Publication number: 20150263103
    Abstract: A semiconductor device according to an embodiment includes a first semiconductor layer including a first nitride semiconductor, a second semiconductor layer on the first semiconductor layer including a second nitride semiconductor, a source electrode, a drain electrode, a first gate electrode provided on the second semiconductor layer between the source electrode and the drain electrode having a schottky junction, a second gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the source electrode and the first gate electrode, electrically connected with the first gate electrode, and a third gate electrode provided above the second semiconductor layer intervening an insulating film, provided between the drain electrode and the first gate electrode, electrically connected with the first gate electrode.
    Type: Application
    Filed: March 17, 2014
    Publication date: September 17, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Takaaki Yasumoto, Naoko Yanase, Tasuku Ono
  • Publication number: 20150263101
    Abstract: In one embodiment, a semiconductor device includes a semiconductor chip including a nitride semiconductor layer, and including a control electrode, a first electrode and a second electrode provided on the nitride semiconductor layer. The device further includes a support including a substrate, and including a control terminal, a first terminal and a second terminal provided on the substrate. The semiconductor chip is provided on the support such that the control electrode, the first electrode and the second electrode face the support. The control electrode, the first electrode and the second electrode of the semiconductor chip are electrically connected to the control terminal, the first terminal and the second terminal of the support, respectively.
    Type: Application
    Filed: September 10, 2014
    Publication date: September 17, 2015
    Inventors: Shingo Masuko, Takaaki Yasumoto, Naoko Yanase, Miki Yumoto, Masahito Mimura, Yasunobu Saito, Akira Yoshioka, Hidetoshi Fujimoto, Takeshi Uchihara, Tetsuya Ohno, Toshiyuki Naka, Tasuku Ono
  • Publication number: 20150263154
    Abstract: A semiconductor device includes a first and second nitride semiconductor layer. The second nitride semiconductor layer has a band gap larger the first nitride semiconductor layer. Source and drain electrodes are formed spaced from each other on the second nitride semiconductor layer. A third nitride semiconductor layer is formed on the second nitride semiconductor layer between the source and drain electrodes. A gate electrode is formed on the third nitride semiconductor layer. The third nitride semiconductor layer comprises at least two first layers and at least one a second layer which has a lower p-type dopant concentration than the first layer. The second layer also has a band gap larger than the first layer. The lowermost layer and the uppermost layer in the third nitride semiconductor layer stack are the first layers.
    Type: Application
    Filed: August 29, 2014
    Publication date: September 17, 2015
    Inventor: Hidetoshi FUJIMOTO
  • Patent number: 9098496
    Abstract: Map data includes, for each of multiple links used for representing a road in a map, a link record and a speed limit record for a certain link. The link records and the speed limit records of the multiple links for representing a road are collected to form separate data lists of respective attribute types, that is, a link record data list and a speed limit record data list, instead of collecting records by a unit of each link. The map data structured as separate attribute data lists of respective attribute data types for links in the map data, for example, establishes inter-attribute data association between different attribute data types for the certain link based on the arrangement orders of the respective attribute data types in the data list indicative of the same arrangement order of the multiple links.
    Type: Grant
    Filed: January 26, 2011
    Date of Patent: August 4, 2015
    Assignee: DENSO CORPORATION
    Inventors: Takayuki Matsunaga, Hidetoshi Fujimoto
  • Patent number: 9091556
    Abstract: A map data is disclosed. The map data comprises a link data and a segment data. The link data describes a characteristic of each link in a group of links on a link-by-link basis. The group of links forms a road network. The segment data relates to each segment in a group of segments on a segment-by-segment basis. The segments are defined in units of link string. Each link string is a string of multiple links and corresponds to a main road. Each link string terminates at least at an intersection of the main road. The multiple links are a part of the group of links. The segment data of each segment describes information on a storage destination of the link data corresponding to the link string that forms the each segment.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: July 28, 2015
    Assignee: DENSO CORPORATION
    Inventor: Hidetoshi Fujimoto
  • Patent number: 9082691
    Abstract: A nitride semiconductor device includes a substrate, a first Inx1Ga1-x1-y1Aly1N layer, a second Inx2Ga1-x2-y2Aly2N layer, an interlayer insulating film, a source electrode, a drain electrode, a first gate electrode, a Schottky electrode, a second gate electrode, an interconnection layer. The second Inx2Ga1-x2-y2Aly2N layer is provided on a surface of the first Inx1Ga1-x1-y1Aly1N layer. The second Inx2Ga1-x2-y2Aly2N layer has a wider band gap than the first Inx1Ga1-x1-y1Aly1N layer. The first gate electrode is provided between the source electrode and the drain electrode on a surface of the second Inx2Ga1-x2-y2Aly2N layer. The Schottky electrode is provided on the second Inx2Ga1-x2-y2Aly2N layer between the first gate electrode and the drain electrode. The second gate electrode is provided on the second Inx2Ga1-x2-y2Aly2N layer between the Schottky electrode and the drain electrode. The interconnection layer electrically connects the source electrode, the Schottky electrode, and the second gate electrode.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: July 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Wataru Saito
  • Patent number: 9054171
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Patent number: 9048304
    Abstract: In a semiconductor device, a first-layer includes a group-III nitride semiconductor of a first conduction type. A second-layer includes a group-III nitride semiconductor of a second conduction type on a first surface of the first layer. A third-layer includes an Al-containing group-III nitride semiconductor on a first region of a surface of the second layer. A gate electrode has one end above a surface of the third-layer and has the other end within the first-layer via the second-layer. The gate electrode is insulated from the first- to third-layers. A first electrode is connected to the third-layer. A second electrode is connected to a second region of the surface of the second-layer. A third electrode is provided above a second surface of the first layer. The second surface is opposite to the first surface of the first layer.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 2, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi Fujimoto