Patents by Inventor Hidetoshi Fujimoto

Hidetoshi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9035320
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a first electrode, a first electrode and a conducting section. The substrate includes a conductive region and has a first surface. The first semiconductor region is provided on the first surface side of the substrate and includes AlXGa1-XN (0?X?1). The second semiconductor region is provided on a side opposite to the substrate of the first semiconductor region and includes AlYGa1-YN (0?Y?1, X?Y). The first electrode is provided on a side opposite to the first semiconductor region of the second semiconductor region and ohmically connects to the second semiconductor region. The conducting section electrically connects between the first electrode and the conductive region.
    Type: Grant
    Filed: August 20, 2013
    Date of Patent: May 19, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Akira Yoshioka, Wataru Saito, Toshiyuki Naka
  • Patent number: 9029915
    Abstract: A semiconductor device includes: a first semiconductor layer made of an AlxGa1-xN (0?x<1); a second semiconductor layer provided on the first semiconductor layer and made of an undoped or first conductivity type AlyGa1-yN (0<y?1, x<y); an anode electrode and a cathode electrode which are connected to the second semiconductor layer; and a third semiconductor layer of second conductivity type provided between the anode electrode and the cathode electrode when viewed from a direction perpendicular to an upper surface of the second semiconductor layer. The third semiconductor layer is depleted when a predetermined magnitude or more of voltage is applied between the anode electrode and the cathode electrode.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: May 12, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Hidetoshi Fujimoto, Takao Noda, Yasunobu Saito, Tomohiro Nitta
  • Publication number: 20150123141
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first electrode, a second electrode, a third electrode, a first insulating film and a second insulating film. The first semiconductor layer includes a nitride semiconductor. The second semiconductor layer is provided on the first layer, includes a nitride semiconductor, and includes a hole. The first electrode is provided in the hole. The second electrode is provided on the second layer. The third electrode is provided on the second layer so that the first electrode is disposed between the third and second electrodes. The first insulating film is provided between the first electrode and an inner wall of the hole and between the first and second electrodes, and is provided spaced from the third electrode. The second insulating film is provided in contact with the second layer between the first and third electrodes.
    Type: Application
    Filed: January 9, 2015
    Publication date: May 7, 2015
    Inventors: Akira YOSHIOKA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Tetsuya OHNO, Wataru SAITO, Toru SUGIYAMA
  • Patent number: 9026368
    Abstract: A vehicle navigation system includes: a route guidance element for searching an optimum route from a current position of a vehicle to a destination according to a normal map data and for guiding the optimum route by displaying the optimum route on a map screen image of a display; a deviation route retrieving element for retrieving a deviation route, which has a possibility that a user may deviate from the optimum route and enter into the deviation route although the vehicle is incapable of driving along the deviation route; and an attention notification element for outputting attention notification information in order to prevent the user from entering into the deviation route when the route guidance element guides the optimum route.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: May 5, 2015
    Assignee: Denso Corporation
    Inventors: Hidetoshi Fujimoto, Yasuhiro Shimizu
  • Patent number: 9006790
    Abstract: According to one embodiment a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: April 14, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
  • Publication number: 20150076506
    Abstract: This disclosure provides a semiconductor device which includes a GaN-based semiconductor layer having a surface with an angle of not less than 0 degree and not more than 5 degrees with respect to an m-plane or an a-plane, a first electrode provided above the surface and having a first end, and a second electrode provided above the surface to space apart from the first electrode, having a second end facing the first end, and a direction of a segment connecting an arbitrary point of the first end and an arbitrary point of the second end is different from a c-axis direction of the GaN-based semiconductor layer.
    Type: Application
    Filed: March 17, 2014
    Publication date: March 19, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takaaki Yasumoto, Naoko Yanase, Kazuhide Abe, Takeshi Uchihara, Yasunobu Saito, Toshiyuki Naka, Akira Yoshioka, Tasuku Ono, Tetsuya Ohno, Hidetoshi Fujimoto, Shingo Masuko, Masaru Furukawa, Yasunari Yagi, Miki Yumoto, Atsuko Iida
  • Publication number: 20150069468
    Abstract: In one embodiment, a semiconductor device includes a first semiconductor layer of a first conductivity type or an intrinsic type. The device further includes a second semiconductor layer of the first conductivity type or the intrinsic type disposed above the first semiconductor layer. The device further includes a third semiconductor layer of a second conductivity type including a first upper portion in contact with the first semiconductor layer, a second upper portion located at a lower position than the first upper portion, a first side portion located between the first upper portion and the second upper portion, and a second side portion located at a lower position than the first side portion.
    Type: Application
    Filed: March 7, 2014
    Publication date: March 12, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tetsuya Ohno, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Takeshi Uchihara, Toshiyuki Naka, Takaaki Yasumoto, Naoko Yanase, Shingo Masuko, Tasuku Ono
  • Patent number: 8963204
    Abstract: According to one embodiment, a semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, an insulating film, an ohmic electrode, and a Schottky electrode. A surface region of the third nitride semiconductor layer between the ohmic electrode and the Schottky electrode contains an element heterogeneous with the constituent element of the third nitride semiconductor layer at a higher concentration than a region of the third nitride semiconductor layer of the second nitride semiconductor layer side.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: February 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Toshiyuki Naka
  • Publication number: 20150034904
    Abstract: In a semiconductor device, a first-layer includes a group-III nitride semiconductor of a first conduction type. A second-layer includes a group-III nitride semiconductor of a second conduction type on a first surface of the first layer. A third-layer includes an Al-containing group-III nitride semiconductor on a first region of a surface of the second layer. A gate electrode has one end above a surface of the third-layer and has the other end within the first-layer via the second-layer. The gate electrode is insulated from the first- to third-layers. A first electrode is connected to the third-layer. A second electrode is connected to a second region of the surface of the second-layer. A third electrode is provided above a second surface of the first layer. The second surface is opposite to the first surface of the first layer.
    Type: Application
    Filed: March 4, 2014
    Publication date: February 5, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hidetoshi FUJIMOTO
  • Publication number: 20150034903
    Abstract: A semiconductor device includes a first layer made of a group III nitride semiconductor of a first conductivity type, a second layer made of a group III nitride semiconductor of a second conductivity type on a first surface of the first layer, a third layer made of a group III nitride semiconductor of the first conductivity type on a first region of a surface of the second layer, a gate electrode extending through the second layer and the third layer and the first surface of the first layer, and insulated from the first, second, and third layers, a first electrode in contact with the third layer, a second electrode in contact with a second region of the surface of the second layer that is different from the first region, and a third electrode provided on a side of a second surface of the first layer.
    Type: Application
    Filed: February 28, 2014
    Publication date: February 5, 2015
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hidetoshi FUJIMOTO, Yasunobu SAITO, Akira YOSHIOKA
  • Patent number: 8928039
    Abstract: According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, Toshiyuki Naka
  • Patent number: 8860090
    Abstract: A nitride semiconductor device includes a first semiconductor layer, a second semiconductor layer, a conductive substrate, a first electrode, a second electrode, and a control electrode. The second semiconductor layer is directly bonded to the first semiconductor layer. The conductive substrate is provided on and electrically connected to the first semiconductor layer. The first electrode and the second electrode are provided on and electrically connected to a surface of the second semiconductor layer on a side opposite to the first semiconductor layer. The control electrode is provided on the surface of the second semiconductor layer between the first electrode and the second electrode. The first electrode is electrically connected to a drain electrode of a MOSFET formed of Si. The control electrode is electrically connected to a source electrode of the MOSFET. The conductive substrate is electrically connected to a gate electrode of the MOSFET.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: October 14, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno
  • Publication number: 20140284610
    Abstract: According to an embodiment, a semiconductor device includes a conductive substrate, a Schottky barrier diode, and a field-effect transistor. The Schottky barrier diode is mounted on the conductive substrate and includes an anode electrode and a cathode electrode. The anode electrode is electrically connected to the conductive substrate. The field-effect transistor is mounted on the conductive substrate and includes a source electrode, a drain electrode, and a gate electrode. The source electrode of the field-effect transistor is electrically connected to the cathode electrode of the Schottky barrier diode. The gate electrode of the field-effect transistor is electrically connected to the anode electrode of the Schottky barrier diode.
    Type: Application
    Filed: August 30, 2013
    Publication date: September 25, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira YOSHIOKA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Takeshi UCHIHARA, Naoko YANASE, Toshiyuki NAKA, Tetsuya OHNO, Tasuku ONO
  • Publication number: 20140246700
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion.
    Type: Application
    Filed: May 12, 2014
    Publication date: September 4, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu SAITO, Hidetoshi FUJIMOTO, Tetsuya OHNO, Akira YOSHIOKA, Wataru SAITO
  • Patent number: 8759878
    Abstract: According to one embodiment, a nitride semiconductor device includes a first semiconductor, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a first electrode, a second electrode and a third electrode. The first, second and fourth semiconductor layers include a nitride semiconductor. The second semiconductor layer is provided on the first semiconductor layer, has a band gap not less than that of the first semiconductor layer. The third semiconductor layer is provided on the second semiconductor layer. The third semiconductor layer is GaN. The fourth semiconductor layer is provided on the third semiconductor layer to have an interspace on a part of the third semiconductor layer, has a band gap not less than that of the second semiconductor layer. The first electrode is provided on a portion of the third semiconductor layer. The fourth semiconductor layer is not provided on the portion.
    Type: Grant
    Filed: September 21, 2011
    Date of Patent: June 24, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Akira Yoshioka, Wataru Saito
  • Publication number: 20140077217
    Abstract: According to one embodiment, a semiconductor device includes a substrate, a first semiconductor region, a second semiconductor region, a first electrode, a first electrode and a conducting section. The substrate includes a conductive region and has a first surface. The first semiconductor region is provided on the first surface side of the substrate and includes AlXGa1-XN (0?X?1). The second semiconductor region is provided on a side opposite to the substrate of the first semiconductor region and includes AlYGa1-YN (0?Y?1, X?Y). The first electrode is provided on a side opposite to the first semiconductor region of the second semiconductor region and ohmically connects to the second semiconductor region. The conducting section electrically connects between the first electrode and the conductive region.
    Type: Application
    Filed: August 20, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno, Akira Yoshioka, Wataru Saito, Toshiyuki Naka
  • Publication number: 20140077263
    Abstract: According to one embodiment, a semiconductor device includes a first nitride semiconductor layer, a second nitride semiconductor layer, a third nitride semiconductor layer, an insulating film, an ohmic electrode, and a Schottky electrode. A surface region of the third nitride semiconductor layer between the ohmic electrode and the Schottky electrode contains an element heterogeneous with the constituent element of the third nitride semiconductor layer at a higher concentration than a region of the third nitride semiconductor layer of the second nitride semiconductor layer side.
    Type: Application
    Filed: March 5, 2013
    Publication date: March 20, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira YOSHIOKA, Yasunobu SAITO, Hidetoshi FUJIMOTO, Tetsuya OHNO, Toshiyuki NAKA
  • Patent number: 8664696
    Abstract: According to one embodiment, a nitride semiconductor device includes a first, a second and a third semiconductor layer, a first and a second main electrode and a control electrode. The first layer made of a nitride semiconductor of a first conductivity type is provided on a substrate. The second layer made of a nitride semiconductor of a second conductivity type is provided on the first layer. The third layer made of a nitride semiconductor is provided on the second layer. The first electrode is electrically connected with the second layer. The second electrode is provided at a distance from the first electrode and electrically connected with the second layer. The control electrode is provided within a first trench via an insulating film. The first trench is disposed between the first and the second main electrodes, penetrates the third and the second layers, and reaches the first layer.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 4, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akira Yoshioka, Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Tetsuya Ohno
  • Publication number: 20140035004
    Abstract: According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.
    Type: Application
    Filed: October 8, 2013
    Publication date: February 6, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Wataru SAITO, Yasunobu SAITO, Hidetoshi FUJIMOTO, Akira YOSHIOKA, Tetsuya OHNO, Toshiyuki NAKA
  • Publication number: 20140025299
    Abstract: A map data is disclosed. The map data comprises a link data and a segment data. The link data describes a characteristic of each link in a group of links on a link-by-link basis. The group of links forms a road network. The segment data relates to each segment in a group of segments on a segment-by-segment basis. The segments are defined in units of link string. Each link string is a string of multiple links and corresponds to a main road. Each link string terminates at least at an intersection of the main road. The multiple links are a part of the group of links. The segment data of each segment describes information on a storage destination of the link data corresponding to the link string that forms the each segment.
    Type: Application
    Filed: September 24, 2013
    Publication date: January 23, 2014
    Applicant: DENSO CORPORATION
    Inventor: Hidetoshi FUJIMOTO