Patents by Inventor Hidetoshi Fujimoto

Hidetoshi Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6204084
    Abstract: The present invention provides a nitride system semiconductor device which decreases in cost and improves productivity without heat treatment after the growth and which increases lifetime and reliability by enhancing the quality of a p-type conductive layer, and a method for manufacturing the nitride system semiconductor device. The nitride system semiconductor device has a multilayer structure of an n-type InxGayAlzB1-x-y-zNmPnAs1-m-n (0≦x, 0≦y 0≦z, 0≦x+y+z≦1, 0<m, 0≦n, 0<m+n≦1) layer, a p-type InxGayAlzB1-x-y-zNmPnAs1-m-n (0≦x, 0≦y, 0≦z, 0≦x+y+z≦1, 0<m, 0<n, 0<m+n≦1) layer, and an electrode 22 formed on a substrate. The oxygen concentration of the surface of the p-type InxGayAlzB1-x-y-zNmPnAs1-m-n layer is 5×1018 cm−3 or lower.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: March 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Lisa Sugiura, Mariko Suzuki, Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, John Rennie, Hideto Sugawara
  • Patent number: 6184799
    Abstract: Monitoring and control apparatus for fail-safe monitoring for normal operation of traffic signal lights provided at an intersection or the like where a plurality of roads intersect. The illumination conditions of respective signal lights are detected using as sensor device, and when the number of illuminated or non-illuminated signal lights is a predetermined number, a normal judgment output of logic value 1 corresponding to a high energy condition is generated while, when the number of illuminated or non-illuminated signal lights is not the predetermined number, an abnormal judgment output of logic value 0 corresponding to a low energy condition is generated. As a result, when a fault in the monitoring apparatus stops the output, the resultant output condition is the same as for a danger condition due to a signal light abnormality, resulting in an extremely safe signal light monitoring and control with excellent fail-safe characteristics.
    Type: Grant
    Filed: December 17, 1996
    Date of Patent: February 6, 2001
    Assignee: The Nippon Signal Co., Ltd.
    Inventors: Yoshitaka Jinno, Yoshiharu Ozaki, Norihiro Okada, Heisaku Mazawa, Hidetoshi Fujimoto, Junya Toda, Koichi Futsuhara, Norihiro Asada
  • Patent number: 6147364
    Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.
    Type: Grant
    Filed: November 20, 1998
    Date of Patent: November 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, Mariko Suzuki, Lisa Sugiura
  • Patent number: 6121634
    Abstract: In a nitride compound semiconductor light emitting device, an In.sub.0.3 Ga.sub.0.7 N/GaN multi-quantum well active layer 105 or an In.sub.0.1 Ga.sub.0.9 N/GaN multi-quantum well adjacent layer 104 is made as a saturable absorptive region so that self-pulsation occurs there. Thus, the device ensures self-pulsation with a high probability with a simple structure, and satisfies requirements for use as an optical head for reading data from an optical disc.
    Type: Grant
    Filed: February 20, 1998
    Date of Patent: September 19, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Saito, Genichi Hatakoshi, Masaaki Onomura, Hidetoshi Fujimoto, Norio Iizuka, Chiharu Nozaki, Johji Nishio, Masayuki Ishikawa
  • Patent number: 6118801
    Abstract: A gallium nitride-based compound semiconductor laser has a double-heterojunction structure, in which an active layer is sandwiched between cladding layers, on a sapphire substrate. A GaN current blocking layer having a striped opening portion is formed on the p-cladding layer. A p-GaN buried layer and a contact layer through which a current is injected into the opening portion of the current blocking layer and which are larger in area than the opening portion are formed. The active layer has a multiple quantum well structure constituted by a cyclic structure formed by cyclically stacking two types of InGaAlN layers which have different band gaps and are 10 nm or more thick.
    Type: Grant
    Filed: August 13, 1999
    Date of Patent: September 12, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Masahiro Yamamoto, Shinya Nunoue, Johji Nishio, Genichi Hatakoshi, Hidetoshi Fujimoto
  • Patent number: 6119066
    Abstract: When a vehicle is within a predetermined distance from an intersection during the execution of navigation operations, a navigation system displays an enlarged guide map of the same intersection. The guide map shows direction labels that are set for roads that are connected to a road to be approached by the vehicle. The direction labels are set for the connecting roads by tracking the connecting roads and by determining appropriate direction labels following a predetermined procedure. For example, names of tollgates, names of stations, names of special facilities, names of administrative units, names of highways or the like may be set as direction labels.
    Type: Grant
    Filed: August 27, 1997
    Date of Patent: September 12, 2000
    Assignee: Denso Corporation
    Inventors: Wataru Sugiura, Osamu Kanematsu, Hidetoshi Fujimoto
  • Patent number: 6080599
    Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.
    Type: Grant
    Filed: June 2, 1998
    Date of Patent: June 27, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Yamamoto, Hidetoshi Fujimoto, Yoshihiro Kokubun, Masayuki Ishikawa, Shinji Saito, Yukie Nishikawa, John Rennie
  • Patent number: 6057565
    Abstract: In the semiconductor light emitting device, a high resistance layer formed by mutual diffusion at an interface with the substrate crystal can be eliminated, and a low resistance p-type contact can be realized. In addition, it is possible to reduce the leak current when an internal current-blocking structure is formed. In practice, a compound semiconductor layer offset in composition ratio stoichiometrically is used as the contact layer. Further, when a predetermined element is added to the contact layer, a large amount of doping can be enabled in comparison with when impurities are added to the ordinary GaN based layer. Therefore, a high concentration conductive type layer can be realized while reducing the contact resistance. In addition, when the compound semiconductor layer offset away from the stoichiometric composition is used as the current-blocking layer, the current-blocking efficiency can be improved.
    Type: Grant
    Filed: September 25, 1997
    Date of Patent: May 2, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Yoshida, Masayuki Ishikawa, Hidetoshi Fujimoto, Yoshihiro Kokubun, Genichi Hatakoshi
  • Patent number: 5998810
    Abstract: A semiconductor light-emitting diode exhibiting an oscillation wavelength of 450 nm or less and comprising a substrate, a lower clad layer formed on or above the substrate and mainly composed of a III-V Group compound semiconductor, an active layer formed directly on the lower clad layer and mainly composed of a III-V Group compound semiconductor, and an upper p-type clad layer formed directly on the active layer and mainly composed of a III-V Group compound semiconductor. This semiconductor light-emitting diode is characterized in that the upper p-type clad layer contains Mg, Si and at least one impurities for compensating residual donors.
    Type: Grant
    Filed: November 28, 1997
    Date of Patent: December 7, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ako Hatano, Yasuo Ohba, Hidetoshi Fujimoto, Kazuhiko Itaya, Johji Nishio
  • Patent number: 5994205
    Abstract: A top surface of a wafer, at which semiconductor devices are formed, is bonded to an auxiliary plate by means of a first wax. In a state where the auxiliary plate is bonded to a polishing jig by means of a second wax, a bottom surface of the wafer, at which a sapphire substrate is provided, is polished. The second wax is melted and the auxiliary plate is removed from the polishing jig. In this state, scribe lines are formed in the bottom surface of the wafer according to a device separation pattern. Then, the bottom surface of the wafer is attached to an adhesive sheet, following which the first wax is melted and the wafer is removed from the auxiliary plate 105. Subsequently, the adhesive sheet is extended and the wafer is divided into the devices along the scribe lines.
    Type: Grant
    Filed: February 2, 1998
    Date of Patent: November 30, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Yamamoto, Hidetoshi Fujimoto
  • Patent number: 5987048
    Abstract: A gallium nitride-based compound semiconductor laser has a double-heterojunction structure, in which an active layer is sandwiched between cladding layers, on a sapphire substrate. A GaN current blocking layer having a striped opening portion is formed on the p-cladding layer. A p-GaN buried layer and a contact layer through which a current is injected into the opening portion of the current blocking layer and which are larger in area than the opening portion are formed. The active layer has a multiple quantum well structure constituted by a cyclic structure formed by cyclically stacking two types of InGaAlN layers which have different band gaps and are 10 nm or more thick.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: November 16, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masayuki Ishikawa, Masahiro Yamamoto, Shinya Nunoue, Johji Nishio, Genichi Hatakoshi, Hidetoshi Fujimoto
  • Patent number: 5966396
    Abstract: A semiconductor laser is formed from a gallium nitride-based compound semiconductor material, and has a double-heterostructure portion obtained by sandwiching an active layer between an n-type cladding layer and a p-type cladding layer on a sapphire substrate. The double-heterostructure portion is formed into a mesa shape on the sapphire substrate via a GaN buffer layer. The two sides of this mesa structure are buried with GaN current blocking layers.
    Type: Grant
    Filed: July 25, 1997
    Date of Patent: October 12, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruhiko Okazaki, Hidetoshi Fujimoto, Masayuki Ishikawa, Shinya Nunoue, Genichi Hatakoshi, Masahiro Yamamoto
  • Patent number: 5932896
    Abstract: The present invention provides a nitride system semiconductor device which decreases cost and improves productivity without heat treatment after the growth and which increases in lifetime and reliability by enhancing the quality of a p-type conductive layer, and a method for manufacturing the nitride system semiconductor device. The nitride system semiconductor device has a multilayer structure of an n-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, a p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n (0.ltoreq.x, 0.ltoreq.y, 0.ltoreq.z, 0.ltoreq.x+y+z.ltoreq.1, 0<m, 0.ltoreq.n, 0<m+n.ltoreq.1) layer, and an electrode 22 formed on a substrate. The oxygen concentration of the surface of the p-type In.sub.x Ga.sub.y Al.sub.z B.sub.1-x-y-z N.sub.m P.sub.n As.sub.1-m-n layer is 5.times.10.sup.18 cm.sup.-3 or lower.
    Type: Grant
    Filed: September 5, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Lisa Sugiura, Mariko Suzuki, Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, John Rennie, Hideto Sugawara
  • Patent number: 5903017
    Abstract: A gallium nitride (GaN)-based semiconductor device comprises a substrate, a single-crystal layer consisting mainly of GaN with a magnesium (Mg) concentration of N.sub.bg1 cm.sup.-3, the single-crystal layer being provided near the substrate and having a thickness of d.sub.1 .mu.m, and a semiconductor layer consisting mainly of Ga.sub.1-x Al.sub.x N having an Al composition x of at least 0.02 and not higher than 1 and having a thickness of d.sub.2 .mu.m. The single-crystal layer is situated between the substrate and the semiconductor layer, and Mg is added to the semiconductor layer at a concentration of N.sub.Mg cm.sup.-3. The Al composition x, the concentration N.sub.Mg, the concentration N.sub.bg1, the thickness d.sub.1 and the thickness d.sub.2 have the following relationshipd.sub.1 /(1600.times.x)<d.sub.2 <3.6.times.10.sup.-3 .times.logN/(x+0.02)+0.02wherein when N.sub.Mg >N.sub.bg1, N cm.sup.-3 =N.sub.Mg -N.sub.bg1, and when N.sub.Mg .ltoreq.N.sub.
    Type: Grant
    Filed: February 20, 1997
    Date of Patent: May 11, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Hidetoshi Fujimoto, Johji Nishio, Mariko Suzuki, Lisa Sugiura
  • Patent number: 5864171
    Abstract: The present invention is intended to provide a semiconductor optoelectric device with high luminescent efficiency and a method of manufacturing the same. The semiconductor optoelectric device 18 according to the present invention is constructed by depositing compound-semiconductor layers 13 and 14 on a monocrystalline substrate 11 of a hexagonal close-packed structure. The shape of the monocrystalline substrate 11 is a parallelogram. Individual sides of the parallelogram are parallel to a <11-20> orientation. As the monocrystalline substrate, sapphire, zinc oxide or silicon carbide may be used. As the compound-semiconductor layers, an n-type GaN layer 13 and p-type GaN layer 14 may be used.
    Type: Grant
    Filed: March 29, 1996
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masahiro Yamamoto, Hidetoshi Fujimoto, Yoshihiro Kokubun, Masayuki Ishikawa, Shinji Saito, Yukie Nishikawa, John Rennie
  • Patent number: 5786606
    Abstract: Disclosed is a semiconductor light-emitting device, comprising a substrate, a thin film formed on the substrate and containing silicon carbide as a main component, a buffer layer formed on the thin film and consisting of a gallium nitride-based material, and a laminate structure formed on the buffer layer and consisting of a plurality of gallium nitride-based material layers, wherein the total thickness of the substrate and the thin film is at least twice the thickness of the buffer layer and is smaller than the thickness of the laminate structure.
    Type: Grant
    Filed: December 12, 1996
    Date of Patent: July 28, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Johji Nishio, Hidetoshi Fujimoto, Kazuhiko Itaya
  • Patent number: 5780873
    Abstract: A semiconductor light-emitting device comprises a semiconductor light-emitting device section of a hexagonal type; and an electrically conductive semiconductor substrate of a cubic type combined into the semiconductor light-emitting device, and having an orientation of its cleavage facet conformed to an orientation of the cleavage facet of one of semiconductor layers forming the semiconductor light-emitting device section. The substrate of the cubic type is cleaved so that the semiconductor light-emitting device section of the hexagonal type is induced to be cleaved, and that a mirror surface can be easily formed.
    Type: Grant
    Filed: August 13, 1996
    Date of Patent: July 14, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuhiko Itaya, Masahiro Yamamoto, Masaaki Onomura, Hidetoshi Fujimoto, Genichi Hatakoshi, Hideto Sugawara, Masayuki Ishikawa, John Rennie, Shinji Saito
  • Patent number: 5752217
    Abstract: Route costs are computed using the Dijkstra algorithm based on link information and connection information and a destination route is set based on a connection of links which has the least route cost. The route cost is set to sub-nodes of each connection link. Therefore, optimal routes can be set even though traffic regulations such as no right turns or the like exist on certain nodes.
    Type: Grant
    Filed: May 24, 1996
    Date of Patent: May 12, 1998
    Assignee: Nippondenso Co., Ltd.
    Inventors: Takashi Ishizaki, Hidetoshi Fujimoto
  • Patent number: D402969
    Type: Grant
    Filed: June 24, 1997
    Date of Patent: December 22, 1998
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hidetoshi Fujimoto
  • Patent number: D431251
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: September 26, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hidetoshi Fujimoto