Abstract: A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.

Abstract: A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.

Abstract: Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. The formation of a buried gate electrode can realize a reduction of the cell area, which is required in a DRAM- and a DRAM/logic-embedded device. This can increase the gate length and reduce the short channel effect. Since an insulating protective film is deposited on the gate electrode, a bit line contact can be formed in self-alignment.

Abstract: A semiconductor device includes a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.

Abstract: A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.

Abstract: A semiconductor device includes an alignment mark which is arranged adjacent to each corner of a semiconductor chip, and a plug which contacts the alignment mark. The alignment mark is formed by part of the uppermost interconnection layer in a multilevel interconnection which is formed on the semiconductor chip and obtained by stacking low-permittivity insulating layers and interconnection layers. The plug is buried in a contact hole formed in the low-permittivity insulating layer below the alignment mark, and contacts the alignment mark.

Abstract: A semiconductor device is disclosed, which comprises a metal fuse formed in a fuse region defined above an element isolation region of a semiconductor substrate; and an interconnection provided under the metal fuse along the metal fuse in plane pattern, and made of a material hard to be blowout by a laser beam irradiated for blowing the metal fuse.

Abstract: Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. The formation of a buried gate electrode can realize a reduction of the cell area, which is required in a DRAM- and a DRAM/logic-embedded device. This can increase the gate length and reduce the short channel effect. Since an insulating protective film is deposited on the gate electrode, a bit line contact can be formed in self-alignment.

Abstract: Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. The formation of a buried gate electrode can realize a reduction of the cell area, which is required in a DRAM- and a DRAM/logic-embedded device. This can increase the gate length and reduce the short channel effect. Since an insulating protective film is deposited on the gate electrode, a bit line contact can be formed in self-alignment.

Abstract: A laminated dummy pattern formed of plural metals including aluminum and tungsten is formed below a fuse or anti-fuse and an influence by application of laser energy at the time of laser blow on an wiring or element can be prevented.

Abstract: In the manufacture of a semiconductor device having a logic section and a memory section built in the same chip, a thin layer of refractory metal (titanium: Ti) is deposited by sputtering in the logic section with the entire memory section covered with a layer of silicon nitride and, when heated subsequently, a layer of silicide (titanium disilicide: TiS2) is formed. Unreacted metal is then removed by means of a wet process, allowing silicide to be formed selectively. In this case, since silicide is not formed on silicon nitride nor silicon oxide, no silicide is formed on diffused layers (source/drain regions of MOSFETs) in the memory section covered with the silicon nitride layer.

Abstract: A method and apparatus for manufacturing pressurized packages capable of obtaining gas displacement pressurized canned goods with high accuracy of internal pressure by atomizing liquid nitrogen, and supplying it together with low temperature vaporized gases to a head space of a can. A spray device assembly (10) for atomizing and spraying the liquid nitrogen is provided in an opening of the bottom of a liquefied gas storage tank (1) formed as a vacuum heat insulating structure. The spray device assembly (10) is constituted such that a valve (2) for controlling the flow rate of liquid nitrogen, a spray nozzle (3), a liquid nitrogen flowpassage (4) extending from the valve (2) to the spray nozzle (3), a nozzle cooling tank (5) for cooling the flowpassage, and a purge device for cutting an outer peripheral portion of a nozzle and an outlet portion off from the air, so as to prevent them from being frosted, are integrally mounted on a spray body 6.

Abstract: Since at least a portion of a trench capacitor electrode is formed by a metal, the electrical sheet resistance of the electrode can be lowered, and the signal propagation time prolonged by CR delay can be shortened. This can reduce the read/write time. The formation of a buried gate electrode can realize a reduction of the cell area, which is required in a DRAM- and a DRAM/logic-embedded device. This can increase the gate length and reduce the short channel effect. Since an insulating protective film is deposited on the gate electrode, a bit line contact can be formed in self-alignment.

Abstract: A semiconductor device has a diffused layer provided on a surface portion of a silicon substrate; an insulating layer provided on the diffused layer and formed with a contact hole at a portion provided with a contact; and a suicide layer provided within said contact hole as a bottom portion of the contact so as to come into contact with the diffused layer, the suicide layer having its bottom surface being flush with or higher than the surf ace of the silicon substrate.

Abstract: A semiconductor device comprises a multiple insulation layer structure in which multiple insulation layers each having interconnection layer are built up and either one of the interconnection layer forming a fuse is blown in order to select a spare cell to relieve a defective cell; and an opening area corresponding to said fuse, the opening being formed on one or more insulation layers disposed above the layer which includes the fuse, wherein a side wall position corresponding to the opening of the first protective insulation film formed on the top layer of the multiple layers and a side wall position corresponding to the opening of the second protective insulation film formed on the first protective insulation film are continuous at the boundary thereof.

Abstract: A laminated dummy pattern formed of plural metals including aluminum and tungsten is formed below a fuse or anti-fuse and an influence by application of laser energy at the time of laser blow on an wiring or element can be prevented.

Abstract: A semiconductor device having a multilayer wire in which a plurality of wires are formed on a semiconductor substrate in layers with insulating films interposed therebetween. An alignment mark made of a conductive material is formed in a layer including an uppermost wire of the multilayer wire. A conductive plug is buried in a contact hole formed in one of the insulating films under the alignment mark. The conductive plug is in contact with the alignment mark.

Abstract: In the manufacture of a semiconductor device having a logic section and a memory section built in the same chip, a thin layer of refractory metal (titanium: Ti) is deposited by sputtering in the logic section with the entire memory section covered with a layer of silicon nitride and, when heated subsequently, a layer of silicide (titanium disilicide: TiS.sub.2) is formed. Unreacted metal is then removed by means of a wet process, allowing silicide to be formed selectively. In this case, since silicide is not formed on silicon nitride nor silicon oxide, no silicide is formed on diffused layers (source/drain regions of MOSFETs) in the memory section covered with the silicon nitride layer.

Abstract: The method of manufacturing a semiconductor device including the step of forming a silicon oxide film on an obverse surface and a reverse surface of a silicon substrate before formation of an element separation region on a semiconductor substrate. Further, the reverse surface of the silicon substrate is exposed by selectively removing only the silicon oxide film formed on the reverse surface of the silicon substrate. A silicon thin film is formed on each of the silicon oxide film and the exposed reverse surface of the silicon substrate, gettering occurring in the silicon thin film formed on the reverse surface of the silicon substrate. The first thin film is formed on each of the silicon thin films. An element separation resist is patterned on the first thin film on the obverse surface of the silicon substrate. The first thin film on the obverse surface of the silicon substrate by etching using the patterned resist as a mask member.

Abstract: A gate oxide layer and a polysilicon layer are formed in sequence over the major surface of a semiconductor substrate. A photoresist layer is formed on the polysilicon layer and an opening is formed in the photoresist layer. Using the photoresist layer as a mask, boron is ion implanted through the polysilicon layer and the gate oxide layer into the semiconductor substrate. Phosphorus is next ion implanted into the polysilicon layer by using the photoresist layer as a mask. Different ion species are ion implanted into the semiconductor substrate and the polysilicon layer, respectively, by using the same photoresist layer, thus decreasing the number of photoetching steps in manufacture of semiconductor devices.