Patents by Inventor Hideyuki Aoki
Hideyuki Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10942187Abstract: A method for selectively and easily quantifying the L-form and/or D-form amino acids to be measured using an aminoacyl tRNA synthetase (AARS) with high sensitivity, and an amino acid quantification kit. A method for quantifying amino acids (L-AA and/or D-AA) in a sample using an AARS, wherein the amino acids and the AARS are released from an aminoacyl AMP-AARS complex once formed, and they are used again for forming the aminoacyl AMP-AARS complex, so that reaction products such as pyrophosphoric acid to be measured can be ultimately produced up to a molar number larger than that of the amino acids contained in the sample, and an amino acid quantification kit for performing the method.Type: GrantFiled: September 28, 2018Date of Patent: March 9, 2021Assignees: IKEDA FOOD RESEARCH CO., LTD., HIROSHIMA CITY UNIVERSITYInventors: Daisuke Sato, Tomoko Nakatsuka, Hideyuki Aoki, Mikiko Kida, Kenta Yamada, Shoji Kaneko, Akimitsu Kugimiya
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Publication number: 20190094235Abstract: [Problem to be solved] It is to provide a method for selectively and easily quantifying the L-form and/or D-form amino acids to be measured using an AARS with high sensitivity, and an amino acid quantification kit. [Solution to Problem] A method for quantifying amino acids (L-AA and/or D-AA) in a sample using an AARS, wherein the amino acids and the AARS are released from an aminoacyl AMP-AARS complex once formed, and they are used again for forming the aminoacyl AMP-AARS complex, so that reaction products such as pyrophosphoric acid to be measured can be ultimately produced up to a molar number larger than that of the amino acids contained in the sample, and an amino acid quantification kit for performing the method.Type: ApplicationFiled: September 28, 2018Publication date: March 28, 2019Applicants: IKEDA FOOD RESEARCH CO., LTD., HIROSHIMA CITY UNIVERSITYInventors: Daisuke SATO, Tomoko NAKATSUKA, Hideyuki AOKI, Mikiko KIDA, Kenta YAMADA, Shoji KANEKO, Akimitsu KUGIMIYA
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Patent number: 9150962Abstract: Provided is a method for producing a substrate with a metal body. This method provides excellent film-forming properties (reflectance and adhesion), is easy to be used on a large substrate, and can be carried out at a low cost. The method includes the steps of: (A) heating a complex to a first temperature so as to generate a vapor of the complex; and (B) contacting the vapor with a substrate heated to a second temperature that is not higher than the first temperature so as to form a metal body containing a central metal of the complex, either in uncombined form or as a compound thereof (exclusive of the complex), on at least part of a surface of the substrate. The second temperature in step (B) is lower than the decomposition temperature of the complex. The central metal of the complex is aluminum or titanium.Type: GrantFiled: January 21, 2014Date of Patent: October 6, 2015Assignee: JSR CORPORATIONInventors: Tatsuya Sakai, Hideki Nishimura, Masahiro Yamamoto, Hisashi Nakagawa, Ryuuichi Saitou, Hideyuki Aoki, Tsuyoshi Furukawa
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Publication number: 20140134331Abstract: Provided is a method for producing a substrate with a metal body. This method provides excellent film-forming properties (reflectance and adhesion), is easy to be used on a large substrate, and can be carried out at a low cost. The method includes the steps of: (A) heating a complex to a first temperature so as to generate a vapor of the complex; and (B) contacting the vapor with a substrate heated to a second temperature that is not higher than the first temperature so as to form a metal body containing a central metal of the complex, either in uncombined form or as a compound thereof (exclusive of the complex), on at least part of a surface of the substrate. The second temperature in step (B) is lower than the decomposition temperature of the complex. The central metal of the complex is aluminum or titanium.Type: ApplicationFiled: January 21, 2014Publication date: May 15, 2014Applicant: JSR CORPORATIONInventors: Tatsuya SAKAI, Hideki NISHIMURA, Masahiro YAMAMOTO, Hisashi NAKAGAWA, Ryuuichi SAITOU, Hideyuki AOKI, Tsuyoshi FURUKAWA
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Patent number: 8496470Abstract: An injection molding die for producing a molded product having an appearance surface, an injection molding method for producing a molded product having an appearance surface, and a resin molded product molded by the injection molding method which is free from occurrence of appearance deficiency such as a flow mark or the like that is a drawback in appearance. A molten thermoplastic resin material is injected into a cavity defined by a molded product's appearance surface forming portion (4a) and a molded product's rear surface forming portion (6a) through one or more direct gates and one or more hot runners to fill the cavity with the molten resin material, thereby performing injection molding.Type: GrantFiled: August 30, 2012Date of Patent: July 30, 2013Assignee: SANKO GOSEI Kabushiki KaishaInventor: Hideyuki Aoki
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Publication number: 20120328731Abstract: An injection molding die for producing a molded product having an appearance surface, an injection molding method for producing a molded product having an appearance surface, and a resin molded product molded by the injection molding method which is free from occurrence of appearance deficiency such as a flow mark or the like that is a drawback in appearance. A molten thermoplastic resin material is injected into a cavity defined by a molded product's appearance surface forming portion (4a) and a molded product's rear surface forming portion (6a) through one or more direct gates and one or more hot runners to fill the cavity with the molten resin material, thereby performing injection molding.Type: ApplicationFiled: August 30, 2012Publication date: December 27, 2012Applicant: SANKO GOSEI Kabushiki KaishaInventor: Hideyuki AOKI
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Patent number: 8298652Abstract: An injection molding die for producing a molded product having an appearance surface, an injection molding method for producing a molded product having an appearance surface, and a resin molded product molded by the injection molding method which is free from occurrence of appearance deficiency such as a flow mark or the like that is a drawback in appearance. A molten thermoplastic resin material is injected into a cavity defined by a molded product's appearance surface forming portion (4a) and a molded product's rear surface forming portion (6a) through one or more direct gates and one or more hot runners to fill the cavity with the molten resin material, thereby performing injection molding.Type: GrantFiled: December 3, 2008Date of Patent: October 30, 2012Assignee: SANKO GOSEI Kabushiki KaishaInventor: Hideyuki Aoki
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Publication number: 20090148672Abstract: An injection molding die for producing a molded product having an appearance surface, an injection molding method for producing a molded product having an appearance surface, and a resin molded product molded by the injection molding method which is free from occurrence of appearance deficiency such as a flow mark or the like that is a drawback in appearance. A molten thermoplastic resin material is injected into a cavity defined by a molded product's appearance surface forming portion (4a) and a molded product's rear surface forming portion (6a) through one or more direct gates and one or more hot runners to fill the cavity with the molten resin material, thereby performing injection molding.Type: ApplicationFiled: December 3, 2008Publication date: June 11, 2009Applicant: SANKO GOSEI Kabushiki KaishaInventor: Hideyuki AOKI
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Patent number: 7356742Abstract: A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer (PC). The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out form the measurement PC unit; a plurality of performance boards (PFBs) mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations.Type: GrantFiled: April 18, 2005Date of Patent: April 8, 2008Assignees: Renesas Technology Corp., Hitachi High-Technologies CorporationInventors: Hideyuki Aoki, Takeshi Wada, Masaaki Namba, Noboru Uchida, Shigeki Katsumi, Yuji Wada, Masaaki Mochiduki
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Patent number: 7341133Abstract: A hydraulic power transmission is provided with a frictional engagement element as a lock-up clutch between a hydraulic power transmission chamber, housing a pump impeller and a turbine runner, and a servo oil chamber of the lock-up clutch. A lock-up oil passage that supplies lock-up hydraulic pressure to the servo oil chamber is connected to a hydraulic pressure supply circuit that is used in common with a circulation oil passage that supplies hydraulic pressure for circulation to the hydraulic power transmission chamber. An orifice is disposed in the circulation oil passage. It is thus possible to perform lock-up with different supply pressures. A common oil supply for the lock-up oil passage and the circulation oil passage is provided, for example, by disposing a converting circuit that adapts an oil passage connection to hydraulic transmissions with different types of lock-up clutches.Type: GrantFiled: August 10, 2005Date of Patent: March 11, 2008Assignee: Aisin A W Co., Ltd.Inventors: Masahiko Ando, Hideyuki Aoki, Hiroyuki Tsukamoto, Akira Fukatsu, Atsushi Mori, Akira Matsuo, Hideaki Furuta
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Patent number: 7225372Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.Type: GrantFiled: September 27, 2004Date of Patent: May 29, 2007Assignee: Renesas Technology Corp & Hitachi ULSI Systems Co., Ltd.Inventors: Iwao Suzuki, Shuji Kikuchi, Fumie Kobayashi, Hideyuki Aoki
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Patent number: 7200394Abstract: In an information distribution service system comprising a plurality of mobile information terminals, a computer system and a plurality of information-provider terminals, the computer system is provided with a user-information database for registration information categories provided for the mobile information terminals' users each serving as a recipient of an information distribution service rendered by the information distribution service system, an information-provider database for registering locations of the information-provider terminals and information to be distributed by the information-provider terminals as notifications, and a location management unit provided for the purpose of inferring changes in location of each mobile information terminal in a time series by using an inference formula provided in advance for predicting the particular mobile information terminal's moving direction and location on the basis of information on locations of the particular mobile information terminal.Type: GrantFiled: August 20, 2003Date of Patent: April 3, 2007Assignee: Fujitsu LimitedInventors: Hideyuki Aoki, Norio Murakami
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Patent number: 7024604Abstract: A semiconductor device manufacturing process which includes a test process that minimizes the test time for a single wafer, reduces the test cost and improves the throughput. The test system is made up of a wafer which includes plural chips formed with flash memories, a wafer level whole-surface contact device for contact with the whole surface of the wafer, a tester for testing electric characteristics of the wafer, and a BOST board interposed between the tester and the wafer level whole-surface contact device and with chip-by-chip control circuits mounted thereon. Where the test time differs depending on each chip in the wafer, the BOST board controls each test item for each chip so that in a parallel manner for the chips, upon completion of a preceding test, a shift is made to the next test.Type: GrantFiled: October 21, 2002Date of Patent: April 4, 2006Assignee: Renesas Technology CorporationInventor: Hideyuki Aoki
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Patent number: 7018857Abstract: A manufacturing method for improving the yield in a semiconductor manufacturing process and reducing the manufacturing cost produces a semiconductor device that is inexpensively manufactured and has a high reliability by reliably making contact during inspection with a suitable pressing force, while limiting damage to an electrode pad even when many inspected electrodes are inspected. A substrate used for inspection of the semiconductor device has a beam, a probe on the beam having a projecting shape for coming in contact with an electrode (electrode pad) of the semiconductor device, and a secondary electrode electrically connected to the probe through an electrically conductive member disposed on the side of the beam opposed to the side where the probe is provided. In an inspecting process, an inspecting device having a layer having many projections formed in the probe come in contact with the electrode pad of the semiconductor device.Type: GrantFiled: June 12, 2003Date of Patent: March 28, 2006Assignee: Renesas Technology Corp.Inventors: Masatoshi Kanamaru, Takanori Aono, Tatsuya Nagata, Kenji Kawakami, Hideyuki Aoki
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Publication number: 20060032720Abstract: A hydraulic power transmission is provided with a frictional engagement element as a lock-up clutch between a hydraulic power transmission chamber, housing a pump impeller and a turbine runner, and a servo oil chamber of the lock-up clutch. A lock-up oil passage that supplies lock-up hydraulic pressure to the servo oil chamber is connected to a hydraulic pressure supply circuit that is used in common with a circulation oil passage that supplies hydraulic pressure for circulation to the hydraulic power transmission chamber. An orifice is disposed in the circulation oil passage. It is thus possible to perform lock-up with different supply pressures. A common oil supply for the lock-up oil passage and the circulation oil passage is provided, for example, by disposing a converting circuit that adapts an oil passage connection to hydraulic transmissions with different types of lock-up clutches.Type: ApplicationFiled: August 10, 2005Publication date: February 16, 2006Applicant: AISIN AW CO., LTD.Inventors: Masahiko Ando, Hideyuki Aoki, Hiroyuki Tsukamoto, Akira Fukatsu, Atsushi Mori, Akira Matsuo, Hideaki Furuta
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Patent number: 6978295Abstract: A server apparatus comprises an information bubble managing unit for managing bubble data (information bubble) in which space range information including position information in a real physical space is correlated with desired supply information, an extracting unit for extracting supply information of bubble data including retrieval object space range information based on position information on a user terminal, a providing unit for providing the extracted supply information to the user terminal, and an information bubble movement control unit for updating at least position information of the bubble data to virtually move the information bubble in the real physical space. In providing an information service, it is possible to retrieve and refer information in an analog-like operation closer to human sensation in the user terminal by using an information bubble virtually registered in the real physical space, and provide information to many and unspecified users with a less number of information bubbles.Type: GrantFiled: August 28, 2001Date of Patent: December 20, 2005Assignee: Fujitsu LimitedInventors: Yoshinobu Meifu, Keiji Mizuma, Hideyuki Aoki
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Patent number: 6955870Abstract: A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.Type: GrantFiled: October 17, 2002Date of Patent: October 18, 2005Assignee: Hitachi, Ltd.Inventors: Ryuji Kohno, Hideo Miura, Masatoshi Kanamaru, Hiroya Shimizu, Hideyuki Aoki
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Patent number: 6952110Abstract: A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device. The testing process includes bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including probes that come into contact with the test electrodes of the semiconductor device, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; and a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.Type: GrantFiled: September 3, 2004Date of Patent: October 4, 2005Assignee: Renesas Technology CorporationInventors: Ryuji Kohno, Hideo Miura, Masatoshi Kanamaru, Hiroya Shimizu, Hideyuki Aoki
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Publication number: 20050193274Abstract: A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer. The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out from the measurement PC unit; a plurality of PFBs mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chip set LSI on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.Type: ApplicationFiled: April 18, 2005Publication date: September 1, 2005Inventors: Hideyuki Aoki, Takeshi Wada, Masaaki Namba, Noboru Uchida, Shigeki Katsumi, Yuji Wada, Masaaki Mochiduki
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Patent number: 6885208Abstract: A semiconductor device includes a quadrangular semiconductor substrate and a self test circuit formed on the semiconductor substrate. A plurality of pads are formed on the semiconductor substrate, which pads are coupled at least to the self test circuit. The semiconductor substrate includes four rectangular or square regions which each include a respective corner of the quadrangle, and at least two of the pads are respectively located on diagonally opposite ones of the regions from one another.Type: GrantFiled: August 15, 2002Date of Patent: April 26, 2005Assignee: Renesas Technology Corp.Inventors: Toshio Miyatake, Tatsuya Nagata, Hiroya Shimizu, Ryuji Kohno, Hideyuki Aoki