Patents by Inventor Hideyuki Aoki

Hideyuki Aoki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050074910
    Abstract: A manufacturing method for improving the yield in a semiconductor manufacturing process and reducing the manufacturing cost produces a semiconductor device that is inexpensively manufactured and has a high reliability by reliably making contact during inspection with a suitable pressing force, while limiting damage to an electrode pad even when many inspected electrodes are inspected. A substrate used for inspection of the semiconductor device has a beam, a probe on the beam having a projecting shape for coming in contact with an electrode (electrode pad) of the semiconductor device, and a secondary electrode electrically connected to the probe through an electrically conductive member disposed on the side of the beam opposed to the side where the probe is provided. In an inspecting process, an inspecting device having a layer having many projections formed in the probe come in contact with the electrode pad of the semiconductor device.
    Type: Application
    Filed: June 12, 2003
    Publication date: April 7, 2005
    Inventors: Masatoshi Kanamaru, Takanori Aono, Tatsuya Nagata, Kenji Kawakami, Hideyuki Aoki
  • Publication number: 20050044458
    Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.
    Type: Application
    Filed: September 27, 2004
    Publication date: February 24, 2005
    Inventors: Iwao Suzuki, Shuji Kikuchi, Fumie Kobayashi, Hideyuki Aoki
  • Publication number: 20050032252
    Abstract: A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
    Type: Application
    Filed: September 3, 2004
    Publication date: February 10, 2005
    Applicant: Renesas Technology Corporation
    Inventors: Ryuji Kohno, Hideo Miura, Masatoshi Kanamaru, Hiroya Shimizu, Hideyuki Aoki
  • Patent number: 6828810
    Abstract: A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.
    Type: Grant
    Filed: July 30, 2002
    Date of Patent: December 7, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hiroya Shimizu, Naoto Ban, Hideyuki Aoki
  • Patent number: 6826720
    Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: November 30, 2004
    Assignee: Renesas Technology, Corp.
    Inventors: Iwao Suzuki, Shuji Kikuchi, Fumie Kobayashi, Hideyuki Aoki
  • Patent number: 6774654
    Abstract: A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: August 10, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanorr Aono, Ryuji Kohno, Toshio Miyatake, Hideyuki Aoki, Naoto Ban
  • Publication number: 20040127217
    Abstract: In an information distribution service system comprising a plurality of mobile information terminals, a computer system and a plurality of information-provider terminals, the computer system is provided with a user-information database for registration information categories provided for the mobile information terminals' users each serving as a recipient of an information distribution service rendered by the information distribution service system, an information-provider database for registering locations of the information-provider terminals and information to be distributed by the information-provider terminals as notifications, and a location management unit provided for the purpose of inferring changes in location of each mobile information terminal in a time series by using an inference formula provided in advance for predicting the particular mobile information terminal's moving direction and location on the basis of information on locations of the particular mobile information terminal, and the purpos
    Type: Application
    Filed: August 20, 2003
    Publication date: July 1, 2004
    Inventors: Hideyuki Aoki, Norio Murakami
  • Publication number: 20040122700
    Abstract: A network monitor center monitors states of a switch such as an M/C, EPON or the like, a router/sw, etc. that configure a network, and transmits a result of monitoring to a Web portal server; the Web portal server indicates, based on the result of the monitoring by the network monitor center, a content distribution server to change a resolution rate; and a charge center imposes a charge based on a result of having changed the resolution rate.
    Type: Application
    Filed: December 11, 2003
    Publication date: June 24, 2004
    Inventors: Hideyuki Aoki, Eiichiro Takahashi, Hisayuki Sekine
  • Patent number: 6714030
    Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: March 30, 2004
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
  • Patent number: 6660541
    Abstract: A method of manufacturing a semiconductor device includes forming process of forming a semiconductor element on a semiconductor wafer and testing process of testing electrical performance of the formed semiconductor element. The testing process includes process of electrically connecting a testing apparatus to an electrode pad formed on the semiconductor element to be tested. The testing apparatus has a probe-formed substrate including a plurality of beams having probes to be electrically connected to the electrode pads. The probe-formed substrate has a first beam having at least one probe for electrically connection with the electrode pad and a second beam having a number of probes for electrical connection with the electrode pads of which number is more than the number of the electrode pads electrically connected by said first beam.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: December 9, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hideyuki Aoki
  • Publication number: 20030189439
    Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.
    Type: Application
    Filed: March 18, 2003
    Publication date: October 9, 2003
    Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban
  • Publication number: 20030161910
    Abstract: Fermented soybean foods rich in &ggr;-aminobutyric acid are produced by fermentation of soybean using Tempe molds.
    Type: Application
    Filed: November 25, 2002
    Publication date: August 28, 2003
    Inventors: Hideyuki Aoki, Ichiyo Uda, Noriko Miyamoto, Keiko Tagami, Yuji Furuya, Mitsumasa Mankura
  • Publication number: 20030122550
    Abstract: A semiconductor device testing apparatus is realized, which allows contactors to be positioned throughout the wafer surface highly accurately for uniform contact, testing a large-sized wafer, and cost reduction. A plurality of divided contactor blocks is formed with a positioning groove. The groove is used to position the plurality of contactor blocks with a positioning frame. Because the contactor blocks are divided into plurals, it is less likely that a partial surface distortion affects other portions to impair surface flatness as compared with the case where a plurality of non-divided contactors is formed integrally, and the plurality of contactor blocks can be brought into contact with a wafer to be tested uniformly. Additionally, even though abnormality is generated in a part of the contactor blocks, only the part of the contactor blocks is replaced. Therefore, replacement costs can be reduced as compared with the case where a plurality of non-divided contactors is formed integrally.
    Type: Application
    Filed: July 30, 2002
    Publication date: July 3, 2003
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hiroya Shimizu, Naoto Ban, Hideyuki Aoki
  • Publication number: 20030121584
    Abstract: A semiconductor device manufacturing process is disclosed which includes a test process capable of minimizing the test time for a single wafer, thus capable of reducing the test cost and improving the throughput. A test system is used in the semiconductor device test process. The test system is made up of a wafer which comprises plural chips formed with flash memories, a wafer level whole-surface contact device for contact with the whole surface of the wafer, a tester for testing electric characteristics of the wafer, and a BOST board interposed between the tester and the wafer level whole-surface contact device and with chip-by-chip control circuits mounted thereon. In the case where the test time differs depending on each chip in the wafer, the BOST board controls each test item for each chip so that in a parallel manner for the chips, upon completion of a preceding test, a shift is made to the next test.
    Type: Application
    Filed: October 21, 2002
    Publication date: July 3, 2003
    Applicant: Hitachi, Ltd.
    Inventor: Hideyuki Aoki
  • Publication number: 20030113944
    Abstract: A method of manufacturing a semiconductor device includes forming process of forming a semiconductor element on a semiconductor wafer and testing process of testing electrical performance of the formed semiconductor element. The testing process includes process of electrically connecting a testing apparatus to an electrode pad formed on the semiconductor element to be tested. The testing apparatus has a probe-formed substrate including a plurality of beams having probes to be electrically connected to the electrode pads. The probe-formed substrate has a first beam having at least one probe for electrically connection with the electrode pad and a second beam having a number of probes for electrical connection with the electrode pads of which number is more than the number of the electrode pads electrically connected by said first beam.
    Type: Application
    Filed: October 23, 2002
    Publication date: June 19, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanori Aono, Ryuji Kohno, Hideyuki Aoki
  • Publication number: 20030102880
    Abstract: A semiconductor inspecting apparatus having a plurality of electrical connection boards arranged in the inspecting apparatus and a plurality of probes respectively provided on a plurality of beams formed on a first board of said plurality of electrical connection boards, the probes being adapted to be individually brought into contact with a plurality of electrode pads of a semiconductor device for inspection, so as to inspect the semiconductor device while establishing electrical connection therebetween. A one-end supported beam is used as each of the beams, and each of the probes is formed at a portion shifted in a rectangular direction to a center line of a longitudinal direction of the one-end supported beam.
    Type: Application
    Filed: December 12, 2002
    Publication date: June 5, 2003
    Inventors: Masatoshi Kanamaru, Yoshishige Endo, Takanorr Aono, Ryuji Kohno, Toshio Miyatake, Hideyuki Aoki, Naoto Ban
  • Publication number: 20030104641
    Abstract: A method of manufacturing a semiconductor device has forming process for forming a semiconductor device on a major surface of a wafer, and testing process for testing defect of the semiconductor device formed on the wafer. The testing process includes a step bringing a testing apparatus into contact with test electrodes of the semiconductor device. The testing apparatus has a contactor including a plurality of probes that come into contact with the test electrodes of the semiconductor device to be tested, and secondary electrodes electrically connected to the probes and disposed on a surface opposite to the probes; a substrate on which electrodes electrically communicated to the contactor by a conducting device. The conducting device is so formed that stress applied to the conducting device in the state where the probes are in contact with the test electrodes is larger than stress applied to the conducting device in the state where the probes are not in contact with the test electrodes.
    Type: Application
    Filed: October 17, 2002
    Publication date: June 5, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Hideo Miura, Masatoshi Kanamaru, Hiroya Shimizu, Hideyuki Aoki
  • Patent number: 6573112
    Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: June 3, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kono, Akihiko Ariga, Hideyuki Aoki, Hiroyuki Ohta, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Shinji Tanaka, Naoto Ban, Hideo Miura
  • Patent number: 6566149
    Abstract: For an inspection tray, a silicon substrate including a beam or a diaphragm, a probe and wiring is used. To highly accurately position a chip to be inspected, a second substrate for alignment is disposed on the substrate. To position the probe having wiring disposed on the first substrate and the electrode pad of the chip to be inspected, a projection or a groove is formed in each of both substrates. Preferably, the projection or groove should be formed by silicon anisotorpic etching to have a (111) crystal surface. As another machining method, dry etching can be used for machining the positioning projection or groove. By using an inductively coupled plasma-reactive ion etching (ICP-RIE) device for the dry etching, a vertical column or groove can be easily machined.
    Type: Grant
    Filed: March 16, 2001
    Date of Patent: May 20, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Masatoshi Kanamaru, Atsushi Hosogane, Yoshihige Endou, Ryuji Kouno, Hideo Miura, Shinji Tanaka, Hiroyuki Ohta, Akihiko Ariga, Naoto Ban, Hideyuki Aoki
  • Patent number: 6548315
    Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.
    Type: Grant
    Filed: January 29, 2002
    Date of Patent: April 15, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Ryuji Kohno, Hideo Miura, Yoshishige Endo, Masatoshi Kanamaru, Atsushi Hosogane, Hideyuki Aoki, Naoto Ban