Abstract: Realized is a semiconductor device that test can be effectively conducted by the test device even where the semiconductor device is reduced in chip size and hence pad pitch. A plurality of pads are formed on both ends of a semiconductor substrate. An input pad group is arranged at a left end side of the semiconductor device while an input/output pad groups are arranged at a right end side thereof. A BIST circuit is arranged at an upper right area of the semiconductor device, and the pads close to the BIST circuit serve as BIST exclusive pads. Because the area for arranging the pads for BIST is limited due to the increase of input pads and the like and all the pads for BIST cannot be arranged at one end of the semiconductor device, the BIST pads are separately provided in both ends of the semiconductor substrate. Those close to the BIST circuit are provided as exclusive pads while the others are as common-use pads. The pads 3a and 3b are separated to the upper and lower areas of the semiconductor device.

Abstract: A method for manufacturing a semiconductor device includes forming an integrated circuit on a surface of a wafer and testing electric characteristic of the integrated circuit. The testing includes positioning each of probes of a semiconductor testing equipment and each of electrodes of a tested semiconductor element with each other, and allowing each of the probes to come into contact with each of the electrodes. The semiconductor testing equipment includes a first substrate having a cantilever, the probes being formed on the cantilever of the first substrate, and wires for electrically connecting the probes to electrode pads which are formed on an opposite side of the first substrate to a side on which the probes are formed. Each of the wires has a region arranged on an insulating layer, which is formed on the cantilever, on the opposite side.

Abstract: A Web site access service control apparatus as a computer system includes a module for transmitting a content menu of a Web site provided by a non-contract common carrier of a user to a communications terminal of the user in response to a request given from the user via the communications terminal, a module for obtaining content data corresponding to the content menu of the non-contract common carrier selected by the user, and transmitting the content data to the communications terminal, a module for transmitting, to the communications terminal of the user, a menu in which the non-contact common carrier is arbitrarily selected corresponding to the contract-common carrier of the user, and a module for converting display data in accordance with an attribute of the communications terminal of the user.

Abstract: [Problem] To provide a semiconductor device manufacturing method and a semiconductor device inspection method both of which are capable of efficiently inspecting individual LSI chips separated by cutting, as well as a jig for use in such methods.

Abstract: The conventional semiconductor element testing equipment is arranged to position each probe accurately and need a burdensome operation for fixing, and includes only a limited number of electrode pads and chips to be tested at a batch. An equipment for testing a semiconductor element is arranged to keep each of electrode pads formed on a semiconductor element to be tested in direct contact with each of probes formed on a first substrate composed of silicon, one of electric connecting substrates disposed in the equipment. On the first substrate, each probe is formed on a cantilever and a wire is routed from a tip of each probe along a tip of the cantilever to the electrode pad formed on an opposite surface to the probe forming surface through an insulating layer.

Abstract: A structure is provided such that a plural cantilevers are formed on a first board formed of silicon, probes are respectively formed on the individual cantilevers at positions each offset perpendicularly to a longitudinal center line of the cantilever, and wiring connected continuously from each probe to a secondary electrode pad portion through an insulating layer. A structure is alternatively adopted such that by using a both-ends supported beam formed of silicon as the beam, each probe is formed at a position offset toward a supported portion side of the both-ends supported beam.

Abstract: Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

Abstract: A server stores terminal information including an address of each terminal device belonging to a group constituted by a plurality of terminal devices. The server receives, from a terminal device belonging to the group, a distribution request including access information and distribution destination information. The server accesses the distribution information based on the access information, and receives the distribution information. The server specifies an address of a distribution destination terminal device based on the distribution destination information, and distributes the received distribution information to the destination terminal device.

Abstract: A server apparatus comprises an information bubble managing unit for managing bubble data (information bubble) in which space range information including position information in a real physical space is correlated with desired supply information, an extracting unit for extracting supply information of bubble data including retrieval object space range information based on position information on a user terminal, a providing unit for providing the extracted supply information to the user terminal, and an information bubble movement control unit for updating at least position information of the bubble data to virtually move the information bubble in the real physical space. In providing an information service, it is possible to retrieve and refer information in an analog-like operation closer to human sensation in the user terminal by using an information bubble virtually registered in the real physical space, and provide information to many and unspecified users with a less number of information bubbles.

Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: A method for manufacturing a semiconductor device includes forming an integrated circuit on a surface of a wafer and testing electric characteristic of the integrated circuit. The testing includes positioning each of probes of a semiconductor testing equipment and each of electrodes of a tested semiconductor element with each other, and allowing each of the probes to come into contact with each of the electrodes. The semiconductor testing equipment includes a first substrate having a cantilever, the probes being formed on the cantilever of the first substrate, and wires for electrically connecting the probes to electrode pads which are formed on an opposite side of the first substrate to a side on which the probes are formed. Each of the wires has a region arranged on an insulating layer, which is formed on the cantilever, on the opposite side.

Abstract: [Problem] To provide a semiconductor device manufacturing method and a semiconductor device inspection method both of which are capable of efficiently inspecting individual LSI chips separated by cutting, as well as a jig for use in such methods. [Means for Resolution] After a multiplicity of LSI chips are cut and separated from one semiconductor wafer, in the step of inspecting LSI chips, a predetermined number N of chips are rearranged and integrated by using a jig for integration which is formed of a material whose coefficient of thermal expansion approximates that of the chips and in which is formed an accommodating portion for rearranging the predetermined number N of chips, and the integrated predetermined number N of chips are subjected to a predetermined inspection process in a subsequent inspection step, whereby inspection efficiency is improved and inspection costs are reduced.

Abstract: A testing circuit using ALPG is mounted in a testing board in which sockets for mounting semiconductor memories as devices to be tested in the board is mounted and a volatile memory for storing a data table for generating a random pattern is provided in the testing circuit so that a test using a test pattern having no regularity is performed using the data table in addition to a test using a test pattern having regularity generated by the ALPG.

Abstract: A memory test system can screen objects of tests accurately at low cost in quasi-operating conditions by utilizing a personal computer. The system utilizes a PC tester comprising a measurement PC unit that carries a memory module to be used as reference; a signal distribution unit for distributing the signal taken out from the measurement PC unit; a plurality of PFBs mounted with respective objected products to be observed simultaneously by using the signals distributed by the signal distribution unit; a display panel for displaying the current status of the test that is being conducted; a power source for producing the operating voltage of the system; and a control PC for controlling the selection of test parameters and various analytical operations. The PC tester is adapted to take out the signal from the chip set LSI on the PC mother board in the measurement PC unit to the individual memories on the memory module or the memory module per se and test them in quasi-operating conditions.

Abstract: A semiconductor inspection apparatus which is possible to inspect a plurality of semiconductor devices collectively at one time, which has conventionally been difficult because of precision or the like of probes.

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. Input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: A lattice-like delay circuit is configured wherein a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals and respectively form output signals obtained by inverting the input signals inputted to the first and second signals, are used so as to be disposed in lattice form in a first signal transfer direction and a second signal transfer direction. In the lattice-like delay circuit, input clock signals are successively delayed in the first signal transfer direction and thereafter inputted to the respective logic gate circuits extending from the first to the last as seen in the first signal transfer direction. Output signals are obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.

Abstract: A static RAM comprises: column select circuits for connecting a plurality of pairs of corresponding complementary data lines at a unit of each pair with common complementary data lines; and redundant circuits each composed of the complementary data line pair and the column select circuit corresponding to the unit. Load MOSFETs of the complementary data lines are arranged close to the column select circuits to inhibit the column selecting operations by a decoder circuit and turn off the load MOSFETs when fuse means is cut. An access to a defective address is detected by a redundant decoder stored with the defective address, when the fuse means is selectively cut, to select the column select circuits of the redundant circuit.

Abstract: A double-acting hydraulic actuator structure for use in an automatic transmission has a two-layered structure which includes first and second frictional engagement element hydraulic actuators. The first hydraulic actuator includes a drum member and a first piston fitted hermetically and slidably in the drum member. The second hydraulic actuator is formed by the interior of the first piston and a second piston fitted hermetically and slidably mounted within the first piston. The first and second pistons are both urged toward their disengaged positions by the action of a common return spring. A second spring is provided for urging the second piston alone against the force of the return spring.