Patents by Inventor Hideyuki Kishida

Hideyuki Kishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250015197
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Application
    Filed: September 23, 2024
    Publication date: January 9, 2025
    Inventors: Shunpei YAMAZAKI, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Hideyuki KISHIDA
  • Patent number: 12170339
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: December 17, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Hideyuki Kishida
  • Patent number: 12136629
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Grant
    Filed: November 15, 2023
    Date of Patent: November 5, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Hideyuki Kishida
  • Patent number: 12119408
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: October 15, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Hideyuki Kishida
  • Patent number: 12062724
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Grant
    Filed: September 8, 2023
    Date of Patent: August 13, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Hideyuki Kishida
  • Publication number: 20240162234
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Application
    Filed: November 15, 2023
    Publication date: May 16, 2024
    Inventors: Toshikazu KONDO, Hideyuki KISHIDA
  • Patent number: 11967648
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Hideyuki Kishida
  • Publication number: 20240055533
    Abstract: To provide a transistor having a favorable electric characteristics and high reliability and a display device including the transistor. The transistor is a bottom-gate transistor formed using an oxide semiconductor for a channel region. An oxide semiconductor layer subjected to dehydration or dehydrogenation through heat treatment is used as an active layer. The active layer includes a first region of a superficial portion microcrystallized and a second region of the rest portion. By using the oxide semiconductor layer having such a structure, a change to an n-type, which is attributed to entry of moisture to the superficial portion or elimination of oxygen from the superficial portion, and generation of a parasitic channel can be suppressed. In addition, contact resistance between the oxide semiconductor layer and source and drain electrodes can be reduced.
    Type: Application
    Filed: October 25, 2023
    Publication date: February 15, 2024
    Inventors: Shunpei YAMAZAKI, Masayuki SAKAKURA, Ryosuke WATANABE, Junichiro SAKATA, Kengo AKIMOTO, Akiharu MIYANAGA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Publication number: 20230420569
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Hideyuki KISHIDA
  • Publication number: 20230420568
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Application
    Filed: September 8, 2023
    Publication date: December 28, 2023
    Inventors: Shunpei YAMAZAKI, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Hideyuki KISHIDA
  • Patent number: 11824062
    Abstract: In a thin film transistor, an increase in off current or negative shift of the threshold voltage is prevented. In the thin film transistor, a buffer layer is provided between an oxide semiconductor layer and each of a source electrode layer and a drain electrode layer. The buffer layer includes a metal oxide layer which is an insulator or a semiconductor over a middle portion of the oxide semiconductor layer. The metal oxide layer functions as a protective layer for suppressing incorporation of impurities into the oxide semiconductor layer. Therefore, in the thin film transistor, an increase in off current or negative shift of the threshold voltage can be prevented.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: November 21, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshikazu Kondo, Hideyuki Kishida
  • Patent number: 11735904
    Abstract: A cut-off circuit diagnostic device includes a motor control module that controls a motor, and an external safety module that is detachably attached to the motor control module. The motor control module includes: a motor drive unit that has an inverter circuit for controlling a voltage applied to the motor by pulse width modulation control and a drive circuit for driving a power element of the inverter circuit; a cut-off circuit that cuts off power supply to the drive circuit; and a first cut-off circuit diagnostic unit that has a first diagnosis pulse generator for generating a first signal to control the cut-off by the cut-off circuit and that detects whether or not the power supply to the drive circuit is cut off according to the first signal.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: August 22, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hideyuki Kishida, Taro Kishibe
  • Patent number: 11715801
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: August 1, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takuya Hirohashi, Hideyuki Kishida
  • Patent number: 11695080
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: July 4, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Publication number: 20230050036
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Application
    Filed: October 17, 2022
    Publication date: February 16, 2023
    Inventors: Shunpei YAMAZAKI, Masahiro WATANABE, Mitsuo MASHIYAMA, Kenichi OKAZAKI, Motoki NAKASHIMA, Hideyuki KISHIDA
  • Patent number: 11489077
    Abstract: The impurity concentration in the oxide semiconductor film is reduced, and a highly reliability can be obtained.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: November 1, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masahiro Watanabe, Mitsuo Mashiyama, Kenichi Okazaki, Motoki Nakashima, Hideyuki Kishida
  • Publication number: 20220285556
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Application
    Filed: May 20, 2022
    Publication date: September 8, 2022
    Inventors: Shunpei YAMAZAKI, Jun KOYAMA, Masahiro TAKAHASHI, Hideyuki KISHIDA, Akiharu MIYANAGA, Junpei SUGAO, Hideki UOCHI, Yasuo NAKAMURA
  • Patent number: 11367793
    Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: June 21, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Masahiro Takahashi, Hideyuki Kishida, Akiharu Miyanaga, Junpei Sugao, Hideki Uochi, Yasuo Nakamura
  • Publication number: 20220190166
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Inventors: Junichiro SAKATA, Takuya HIROHASHI, Hideyuki KISHIDA
  • Patent number: 11309430
    Abstract: It is an object to provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a semiconductor device including an inverted staggered thin film transistor whose semiconductor layer is an oxide semiconductor layer, a buffer layer is provided over the oxide semiconductor layer. The buffer layer is in contact with a channel formation region of the semiconductor layer and source and drain electrode layers. A film of the buffer layer has resistance distribution. A region provided over the channel formation region of the semiconductor layer has lower electrical conductivity than the channel formation region of the semiconductor layer, and a region in contact with the source and drain electrode layers has higher electrical conductivity than the channel formation region of the semiconductor layer.
    Type: Grant
    Filed: June 19, 2020
    Date of Patent: April 19, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junichiro Sakata, Takuya Hirohashi, Hideyuki Kishida