Patents by Inventor Hideyuki Kojima

Hideyuki Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180156065
    Abstract: A bearing structure includes: a housing; a bearing hole, which is formed in the housing, and receives a bearing configured to axially support a shaft having one end provided with an impeller; a clearance groove, which is formed in an inner circumferential surface of the bearing hole, and communicates with a passage formed on a lower side of the shaft; and an inclined portion formed on an inner wall surface of the clearance groove, which is positioned at least above the shaft.
    Type: Application
    Filed: February 1, 2018
    Publication date: June 7, 2018
    Applicant: IHI Corporation
    Inventors: Kenji BUNNO, Yutaka Uneura, Shinichi Kaneda, Yuichi Daito, Hideyuki Kojima, Tomomi Sugiura, Shunsuke Nishii
  • Publication number: 20170159708
    Abstract: A bearing structure includes: a bearing hole formed in a bearing housing, a semi-floating metal bearing accommodated in the bearing hole and having a pin hole formed therein; a through-hole formed in the bearing housing and facing the pin hole in the semi-floating metal bearing; a regulating member which is inserted into the through-hole and in which a fixed portion is pressed onto an inner surface of the through-hole for the regulating member to be fixed to the bearing housing at a fixed position where a distal end portion is inserted into the pin hole; a regulating hole opened at a base end in the insertion direction of the regulating member and extending at least to the fixed portion toward the distal end side; and a pressing member provided in the regulating hole to expand the regulating hole by pressing an inner surface of the regulating hole.
    Type: Application
    Filed: February 16, 2017
    Publication date: June 8, 2017
    Applicant: IHI Corporation
    Inventors: Yutaka UNEURA, Shinichi Kaneda, Yuichi Daito, Hideyuki Kojima, Tomomi Sugiura
  • Patent number: 9581043
    Abstract: A turbocharger includes: a thrust bearing fixed to a turbocharger main body; and a supply oil passage provided in the turbocharger main body to the thrust bearing. The thrust bearing includes: an insertion hole in which to insert the turbine shaft; pressure receiving portions displaced from one another in phase in a rotational direction of the turbine shaft, and each configured to form an oil film between the pressure receiving portion and the thrust collar to receive a thrust load by use of oil film pressure; and intervening portions each located between two of the pressure receiving portions adjacent in the rotational direction of the turbine shaft, and being further away from the thrust collar than the pressure receiving portions. The intervening portion vertically under the insertion hole at least partially has a surface further away from the thrust collar than the other intervening portions.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: February 28, 2017
    Assignee: IHI Corporation
    Inventors: Yutaka Uneura, Atsushi Koike, Hideyuki Kojima
  • Publication number: 20170045084
    Abstract: A bearing structure includes a bearing holder that has a hollow main body and an oil hole penetrating through from an outer circumferential surface to an inner circumferential surface of the main body to thereby guide a lubricating oil to the inside of the main body, and that is fixed in a bearing housing; two full-floating metal bearings that are arranged separated from each other in the axial direction of the shaft and support the shaft, in the bearing holder; two thrust bearing surfaces each arranged on the outside of two full-floating metal bearings in the axial direction of the shaft; and two collars each arranged on the outside of two thrust bearing surfaces in the axial direction of the shaft and provided for the shaft. The lubricating oil lubricates thrust bearing surfaces after lubricating full-floating metal bearings.
    Type: Application
    Filed: October 31, 2016
    Publication date: February 16, 2017
    Applicant: IHI CORPORATION
    Inventors: YUTAKA UNEURA, SHINICHI KANEDA, YUICHI DAITO, HIDEYUKI KOJIMA, TOMOMI SUGIURA, KENJI BUNNO
  • Publication number: 20170044933
    Abstract: A bearing structure includes a through-hole penetrating through in the axial direction of shaft, a bearing holder accommodated in the through-hole, a semi-floating metal bearing accommodated in the bearing holder and supporting the shaft inserted into the inside, and a positioning member being inserted into a radial direction of the shaft for both the bearing holder and the semi-floating metal bearing and regulating movement of the semi-floating metal bearing in the axial direction and in a rotating direction of the shaft relative to the bearing holder. For the bearing holder, a press-fit portion to be press-fitted into the through-hole is formed. A gap is formed between at least one of outer circumferential surfaces of both end parts of the bearing holder in the axial direction and the inner circumferential surface of the through-hole.
    Type: Application
    Filed: October 27, 2016
    Publication date: February 16, 2017
    Applicant: IHI CORPORATION
    Inventors: Yutaka UNEURA, Shinichi KANEDA, Yuichi DAITO, Hideyuki KOJIMA, Tomomi SUGIURA
  • Publication number: 20160348719
    Abstract: A bearing structure includes: an outer circumferential groove formed on an outer circumferential surface of a cylindrical portion of a semi-floating metal bearing, and including two opposed surfaces opposed to each other in an axial direction of a shaft and a bottom surface connected to the two opposed surfaces; a radial hole penetrating a wall portion defining the bearing hole so as to communicate with the bearing hole, and facing the outer circumferential groove of the semi-floating metal bearing; a locking member having a body inserted into the radial hole from the outer side of the shaft, wherein at least part of the body is interposed between the two opposed surfaces and fixed to the outer circumferential groove; and an opposed portion provided in the housing, and opposed to the part of the body of the locking member when the locking member is fixed to the outer circumferential groove.
    Type: Application
    Filed: August 10, 2016
    Publication date: December 1, 2016
    Applicant: IHI Corporation
    Inventors: Yutaka UNEURA, Shinichi KANEDA, Hideyuki KOJIMA, Tomomi SUGIURA, Yuichi DAITO
  • Publication number: 20160348577
    Abstract: A turbocharger includes: a shaft provided with a small-diameter portion, and two large-diameter portions formed on two sides of the small-diameter portion; and a semi-floating bearing to rotatably support the shaft. The semi-floating bearing includes a cylindrical body into which the shaft is inserted. An inner peripheral surface of the body includes: two bearing surfaces opposed to the large-diameter portions of the shaft; a non-bearing surface located between the two bearing surfaces, having a larger inner diameter than inner diameters of the bearing surfaces; and an oil passage opened to the non-bearing surface to supply lubricant oil to a gap in a radial direction between the non-bearing surface and the shaft. At least one of the two bearing surfaces extends more in an approaching direction of the two bearing surfaces than does the large-diameter portion opposed in the radial direction to the one bearing surface.
    Type: Application
    Filed: August 10, 2016
    Publication date: December 1, 2016
    Applicant: IHI Corporation
    Inventors: Yutaka UNEURA, Yuichi DAITO, Hideyuki KOJIMA, Tomomi SUGIURA
  • Publication number: 20140140865
    Abstract: A turbocharger includes: a thrust bearing fixed to a turbocharger main body; and a supply oil passage provided in the turbocharger main body to the thrust bearing. The thrust bearing includes: an insertion hole in which to insert the turbine shaft; pressure receiving portions displaced from one another in phase in a rotational direction of the turbine shaft, and each configured to form an oil film between the pressure receiving portion and the thrust collar to receive a thrust load by use of oil film pressure; and intervening portions each located between two of the pressure receiving portions adjacent in the rotational direction of the turbine shaft, and being further away from the thrust collar than the pressure receiving portions. The intervening portion vertically under the insertion hole at least partially has a surface further away from the thrust collar than the other intervening portions.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 22, 2014
    Applicant: IHI Corporation
    Inventors: Yutaka Uneura, Atsushi Koike, Hideyuki Kojima
  • Patent number: 8530308
    Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: September 10, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8518795
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: August 27, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jusuke Ogura, Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi
  • Patent number: 8426267
    Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: April 23, 2013
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8324678
    Abstract: The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.
    Type: Grant
    Filed: October 25, 2010
    Date of Patent: December 4, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ogawa, Hideyuki Kojima, Taiji Ema
  • Patent number: 8283729
    Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
    Type: Grant
    Filed: January 20, 2011
    Date of Patent: October 9, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Publication number: 20120208342
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
    Type: Application
    Filed: April 25, 2012
    Publication date: August 16, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Jusuke OGURA, Hikaru KOKURA, Hideyuki KOJIMA, Toru ANEZAKI, Hiroyuki OGAWA, Junichi ARIYOSHI
  • Patent number: 8173514
    Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.
    Type: Grant
    Filed: February 12, 2009
    Date of Patent: May 8, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Jusuke Ogura, Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi
  • Patent number: 8158483
    Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: April 17, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8080852
    Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: December 20, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
  • Patent number: 8031297
    Abstract: The present invention provides a color filter comprising a transmission area and reflection area in which at least one color pixel of red, green and blue pixels is formed of the same material, wherein a transparent area having no color layer is formed in a part of the reflection area, at least one sub-area is formed in the transparent area, and the size of the sub-area is 20 ?m or more and 2,000 ?m or less. The present invention also provides a liquid crystal display for both transmission display and reflection display with a cheap manufacturing cost, wherein the difference of chromaticity between the transmission display and reflection display is small, and the surface of the transmission area and reflection area have small step heights.
    Type: Grant
    Filed: December 6, 2005
    Date of Patent: October 4, 2011
    Assignee: Toray Industries, Inc.
    Inventors: Hideyuki Kojima, Tetsuo Yamashita, Shigetaka Kasai, Ikumi Hada, Masahiro Yoshioka, Harushi Nonaka, Hiroyuki Sasaki
  • Publication number: 20110198707
    Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500 ° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.
    Type: Application
    Filed: March 30, 2011
    Publication date: August 18, 2011
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventors: Taiji EMA, Hideyuki KOJIMA, Toru ANEZAKI
  • Patent number: 7977723
    Abstract: A semiconductor device includes a semiconductor substrate, an active region formed in the semiconductor substrate and extending in a first direction, the active region including a transistor sub-region and a capacitor sub-region, a first trench extending around the transistor sub-region, an isolation layer disposed in the first trench, a second trench extending around the capacitor sub-region, a first transistor including a first insulating layer disposed on the transistor sub-region, the first transistor including a first conductive layer disposed on the first insulating layer, and a first capacitor including a second insulating layer extending over the capacitor sub-region and a sidewall of the second trench, the first capacitor including a second conductive layer disposed on the second insulating layer, the active region having an end portion in the first direction opposite to the transistor sub-region and extending across the first capacitor.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: July 12, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ogawa, Jun Lin, Hideyuki Kojima