Patents by Inventor Hideyuki Kojima
Hideyuki Kojima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20110108925Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Applicant: FUJITSU LIMITEDInventors: Tomohiko TSUTSUMI, Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Publication number: 20110111567Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: ApplicationFiled: January 20, 2011Publication date: May 12, 2011Applicant: FUJITSU LIMITEDInventors: Tomohiko TSUTSUMI, Taiji EMA, Hideyuki KOJIMA, Toru ANEZAKI
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Patent number: 7939893Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: GrantFiled: August 11, 2010Date of Patent: May 10, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7936579Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: June 2, 2010Date of Patent: May 3, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Publication number: 20110073950Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: ApplicationFiled: December 10, 2010Publication date: March 31, 2011Applicant: FUJITSU LIMITEDInventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7906819Abstract: The semiconductor device includes the concentration of the impurity of the first conductivity type in a doped channel layer of a first conductivity type in the pass transistor is set at a relatively low value, and pocket regions of the first conductivity type in a pass transistor are formed so as to be relatively shallow with a relatively high impurity concentration.Type: GrantFiled: January 8, 2009Date of Patent: March 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Akihiro Usujima, Hideyuki Kojima
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Publication number: 20110037116Abstract: The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.Type: ApplicationFiled: October 25, 2010Publication date: February 17, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hiroyuki Ogawa, Hideyuki Kojima, Taiji Ema
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Patent number: 7888740Abstract: The semiconductor device includes a first MIS transistor including a gate insulating film 92, a gate electrode 108 formed on the gate insulating film 92 and source/drain regions 154, a second MIS transistor including a gate insulating film 96 thicker than the gate insulating film 92, a gate electrode 108 formed on the gate insulating film 96, source/drain regions 154 and a ballast resistor 120 connected to one of the source/drain regions 154, a salicide block insulating film 146 formed on the ballast resistor 120 with an insulating film 92 thinner than the gate insulating film 96 interposed therebetween, and a silicide film 156 formed on the source/drain regions 154.Type: GrantFiled: November 21, 2007Date of Patent: February 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Tomohiko Tsutsumi, Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Publication number: 20100320543Abstract: A semiconductor device manufacturing method includes, forming isolation region having an aspect ratio of 1 or more in a semiconductor substrate, forming a gate insulating film, forming a silicon gate electrode and a silicon resistive element, forming side wall spacers on the gate electrode, heavily doping a first active region with phosphorus and a second active region and the resistive element with p-type impurities by ion implantation, forming salicide block at 500° C. or lower, depositing a metal layer covering the salicide block, and selectively forming metal silicide layers. The method may further includes, forming a thick and a thin gate insulating films, and performing implantation of ions of a first conductivity type not penetrating the thick gate insulating film and oblique implantation of ions of the opposite conductivity type penetrating also the thick gate insulating film before the formation of side wall spacers.Type: ApplicationFiled: August 11, 2010Publication date: December 23, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Taiji EMA, Hideyuki KOJIMA, Toru ANEZAKI
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Patent number: 7820509Abstract: The method of manufacturing a semiconductor device, including a first region where a transistor including a gate electrode of a stacked structure is formed, a second region where a transistor including a gate electrode of a single-layer structure is formed, and a third region positioned in a boundary part between the first region and the second region, includes: depositing a first conductive film, patterning the first conductive film in the first region and the third region so that the outer edge is positioned in the third region, depositing the second conductive film, patterning the second conductive film to form a control gate in the first region while leaving the second conductive film, covering the second region and having the inner edge positioned inner of the outer edge of the first conductive film, and patterning the second conductive film in the second region to form the gate electrode.Type: GrantFiled: April 20, 2007Date of Patent: October 26, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Ogawa, Hideyuki Kojima, Taiji Ema
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Publication number: 20100238716Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: ApplicationFiled: June 2, 2010Publication date: September 23, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Patent number: 7776659Abstract: A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction.Type: GrantFiled: November 30, 2009Date of Patent: August 17, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Hiroyuki Ogawa, Hideyuki Kojima
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Patent number: 7755928Abstract: A semiconductor device includes a first CMOS inverter, a second CMOS inverter, a first transfer transistor and a second transfer transistor wherein the first and second transfer transistors are formed respectively in first and second device regions defined on a semiconductor device by a device isolation region so as to extend in parallel with each other, the first transfer transistor contacting with a first bit line at a first bit contact region on the first device region, the second transfer transistor contacting with a second bit line at a second bit contact region on the second device region, wherein the first bit contact region is formed in the first device region such that a center of said the bit contact region is offset toward the second device region, and wherein the second bit contact region is formed in the second device region such that a center of the second bit contact region is offset toward the first device region.Type: GrantFiled: February 6, 2009Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Toru Anezaki, Tomohiko Tsutsumi, Tatsuji Araya, Hideyuki Kojima, Taiji Ema
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Publication number: 20100136758Abstract: A method of manufacturing a semiconductor device having a first memory cell array region and a second memory cell array region, the method includes forming an active region on a surface layer of a semiconductor substrate, forming a first word line extending in a first direction on the gate insulating film in the first memory cell array region, and forming a second word line extending in a second direction crossing the first direction on the gate insulating film in the second memory cell array region, wherein the ion implantation into the active region is performed from a direction that is inclined from a direction vertical to the surface of the semiconductor substrate and is oblique with respect to both the first direction and the second direction.Type: ApplicationFiled: November 30, 2009Publication date: June 3, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hiroyuki Ogawa, Hideyuki Kojima
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Publication number: 20100105180Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.Type: ApplicationFiled: December 31, 2009Publication date: April 29, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7671384Abstract: An integrated circuit device comprises a memory cell well formed with a flash memory device, first and second well of opposite conductivity types for formation of high voltage transistors, and third and fourth wells of opposite conductivity types for low voltage transistors, wherein at least one of the first and second wells and at least one of the third and fourth wells have an impurity distribution profile steeper than the memory cell well.Type: GrantFiled: August 24, 2005Date of Patent: March 2, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7605041Abstract: Multiple kinds of transistors exhibiting desired characteristics are manufactured in fewer processes. A semiconductor device includes an isolation region reaching a first depth, first and second wells of first conductivity type, a first transistor formed in the first well and having a gate insulating film of a first thickness, and a second transistor formed in the second well and having a gate insulating film of a second thickness less than the first thickness. The first well has a first impurity concentration distribution having an extremum maximum value only at the depth equal to or greater than the first depth. The second well has a second impurity concentration distribution which is superposition of the first impurity concentration distribution, and another impurity concentration distribution which shows an extremum maximum value at a second depth less than the first depth, the superposition shows also an extremum maximum value at the second depth.Type: GrantFiled: December 7, 2007Date of Patent: October 20, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki
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Patent number: 7592216Abstract: A method of manufacturing a semiconductor device includes forming a first trench in a capacitor device region of a semiconductor substrate, forming a capacitor insulation film over a sidewall surface of the first trench, forming a semiconductor film to cover the first trench, a resistor device region of the semiconductor substrate and a logic device region of the semiconductor substrate, introducing a first impurity element into the semiconductor film formed over the first trench, patterning the semiconductor film to form a top electrode in the capacitor device region, a resistor in the resistor device region and a gate electrode in the logic device region, annealing the semiconductor substrate, and introducing a second impurity element in the resistor.Type: GrantFiled: May 27, 2008Date of Patent: September 22, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Jun Lin, Hiroyuki Ogawa, Hideyuki Kojima
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Publication number: 20090224332Abstract: An n-type embedded layer is formed in an N-LV region of a SRAM cell region after an element isolation insulating film is formed on a p-type Si substrate. Thereafter, a p-well and an n-well are formed. In formation of a channel-doped layer, ion implantation is also performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-LV of a logic circuit region. Ion-implantation is further performed into the N-LV region of the SRAM cell region in parallel with ion implantation into an N-MV of an I/O region.Type: ApplicationFiled: February 9, 2009Publication date: September 10, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Tomohiko Tsutsumi, Toru Anezaki, Hideyuki Kojima, Taiji Ema
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Publication number: 20090215243Abstract: A method of manufacturing a semiconductor device includes forming an isolation region defining an active region in a semiconductor substrate, forming a first insulating film over the semiconductor substrate, forming a second insulating film having etching properties different from those of the first insulating film over the first insulating film, selectively removing the second insulating film from a first region over the active region and the isolation region by dry etching using a fluorocarbon-based etching gas, removing a residual film formed by the dry etching over the first insulating film by exposure in an atmosphere containing oxygen, and selectively removing the first insulating film from the first region by wet etching.Type: ApplicationFiled: February 12, 2009Publication date: August 27, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Jusuke Ogura, Hikaru Kokura, Hideyuki Kojima, Toru Anezaki, Hiroyuki Ogawa, Junichi Ariyoshi