Patents by Inventor Hideyuki Matsuoka
Hideyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240127387Abstract: An information processing apparatus comprises a controller, the controller being configured to execute: acquiring pieces of result data showing movement results of a plurality of users; calculating at least either first evaluation values about convenience in a case of moving in predetermined sections in private vehicles or second evaluation values about convenience in a case of moving in the predetermined sections in public transportation at least based on the pieces of result data; and calculating, for a predetermined area, a score indicating a deviation between convenience in the case of moving in the private vehicles and convenience in the case of moving in the public transportation based on the first and second evaluation values.Type: ApplicationFiled: October 18, 2023Publication date: April 18, 2024Applicant: TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Katsunori TAKAHASHI, Akie SAKIYAMA, Nobuto MATSUDAIRA, Haruna FUKUSHIMA, Yohei MIMURA, Takuya MURAKAMI, Yasushi MATSUOKA, Kazuki NAGASHIMA, Hideyuki KASAI, Toshiyasu MURAYAMA
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Publication number: 20240075672Abstract: It is an object of the present invention to provide a novel production method which makes it possible to obtain a molded product containing a P3HB-based resin through an injection blow molding method and a technique for using such a method. The object is achieved by providing a method for producing a molded product containing a P3HB-based resin, the method including the steps of: (A) plasticizing a resin composition containing a P3HB-based resin; (B) subjecting the plasticized resin composition obtained in the step (A) to injection molding to obtain a preform; and (C) subjecting the preform obtained in the step (B) to blow molding to obtain a molded product.Type: ApplicationFiled: December 21, 2021Publication date: March 7, 2024Applicants: KANEKA CORPORATION, SUNTORY HOLDINGS LIMITEDInventors: Hideyuki SUZUKI, Takashi AKIYAMA, Masanori NISHIYAMA, Yoshiaki MATSUOKA, Nobuo NAKAMURA
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Publication number: 20150214476Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: ApplicationFiled: April 9, 2015Publication date: July 30, 2015Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Patent number: 8890107Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: GrantFiled: November 5, 2009Date of Patent: November 18, 2014Assignee: Renesas Electronics CorporationInventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Patent number: 8866120Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: GrantFiled: December 7, 2011Date of Patent: October 21, 2014Assignee: Renesas Electronics CorporationInventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Patent number: 8859344Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: GrantFiled: December 7, 2011Date of Patent: October 14, 2014Assignee: Renesas Electronics CorporationInventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Publication number: 20120241715Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: ApplicationFiled: June 11, 2012Publication date: September 27, 2012Inventors: YUICHI MATSUI, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Publication number: 20120074377Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: ApplicationFiled: December 7, 2011Publication date: March 29, 2012Inventors: YUICHI MATSUI, Nozomu MATSUZAKI, Norikatsu TAKAURA, Naoki YAMAMOTO, Hideyuki MATSUOKA, Tomio IWASAKI
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Publication number: 20120077325Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: ApplicationFiled: December 7, 2011Publication date: March 29, 2012Inventors: YUICHI MATSUI, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Patent number: 8129707Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.Type: GrantFiled: June 18, 2009Date of Patent: March 6, 2012Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Motoyasu Terao, Kenzo Kurotsuchi, Tsuyoshi Yamauchi
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Patent number: 7838379Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.Type: GrantFiled: January 29, 2009Date of Patent: November 23, 2010Assignee: Hitachi, Ltd.Inventors: Masaharu Kinoshita, Motoyasu Terao, Hideyuki Matsuoka, Yoshitaka Sasago, Yoshinobu Kimura, Akio Shima, Mitsuharu Tai, Norikatsu Takaura
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Patent number: 7834337Abstract: A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145° C. or higher. The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40 at % or more and 65 at % or less in Zn-Ge-Te.Type: GrantFiled: December 20, 2004Date of Patent: November 16, 2010Assignee: Renesas Electronics CorporationInventors: Norikatsu Takaura, Motoyasu Terao, Hideyuki Matsuoka, Kenzo Kurotsuchi
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Patent number: 7829930Abstract: A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal.Type: GrantFiled: July 9, 2008Date of Patent: November 9, 2010Assignee: Hitachi, Ltd.Inventors: Motoyasu Terao, Hideyuki Matsuoka, Naohiko Irie, Yoshitaka Sasago, Riichiro Takemura, Norikatsu Takaura
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Publication number: 20100188877Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.Type: ApplicationFiled: March 26, 2010Publication date: July 29, 2010Inventors: Satoru Hanzawa, Kiyoo Itoh, Hideyuki Matsuoka, Motoyasu Terao, Takeshi Sakata
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Patent number: 7719870Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.Type: GrantFiled: October 25, 2007Date of Patent: May 18, 2010Assignee: Hitachi, Ltd.Inventors: Satoru Hanzawa, Kiyoo Itoh, Hideyuki Matsuoka, Motoyasu Terao, Takeshi Sakata
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Publication number: 20100044672Abstract: Manufacturing processes for phase change memory have suffered from the problem of chalcogenide material being susceptible to delamination, since this material exhibits low adhesion to high melting point metals and silicon oxide films. Furthermore, chalcogenide material has low thermal stability and hence tends to sublime during the manufacturing process of phase change memory. According to the present invention, conductive or insulative adhesive layers are formed over and under the chalcogenide material layer to enhance its delamination strength. Further, a protective film made up of a nitride film is formed on the sidewalls of the chalcogenide material layer to prevent sublimation of the chalcogenide material layer.Type: ApplicationFiled: November 5, 2009Publication date: February 25, 2010Inventors: Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Naoki Yamamoto, Hideyuki Matsuoka, Tomio Iwasaki
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Publication number: 20090267047Abstract: The present invention can promote the large capacity, high performance and high reliability of a semiconductor memory device by realizing high-performance of both the semiconductor device and a memory device when the semiconductor memory device is manufactured by stacking a memory device such as ReRAM or the phase change memory and the semiconductor device. After a polysilicon forming a selection device is deposited in an amorphous state at a low temperature, the crystallization of the polysilicon and the activation of impurities are briefly performed with heat treatment by laser annealing. When laser annealing is performed, the recording material located below the silicon subjected to the crystallization is completely covered with a metal film or with the metal film and an insulating film, thereby making it possible to suppress a temperature increase at the time of performing the annealing and to reduce the thermal load of the recording material.Type: ApplicationFiled: April 27, 2009Publication date: October 29, 2009Inventors: Yoshitaka SASAGO, Riichiro TAKEMURA, Masaharu KINOSHITA, Toshiyuki MINE, Akio SHIMA, Hideyuki MATSUOKA, Mutsuko HATANO, Norikatsu TAKAURA
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Publication number: 20090250680Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.Type: ApplicationFiled: June 18, 2009Publication date: October 8, 2009Applicants: HITACHI, LTD., HITACHI ULSI SYSTEMS CO., LTD.Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Motoyasu Terao, Kenzo Kurotsuchi, Tsuyoshi Yamauchi
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Patent number: 7586782Abstract: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.Type: GrantFiled: February 6, 2008Date of Patent: September 8, 2009Assignee: Renesas Technology Corp.Inventors: Hideyuki Matsuoka, Riichiro Takemura
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Publication number: 20090189137Abstract: In a phase change memory, electric property of a diode used as a selection device is extremely important. However, since crystal grain boundaries are present in the film of a diode using polysilicon, it involves a problem that the off leak property varies greatly making it difficult to prevent erroneous reading. For overcoming the problem, the present invention provides a method of controlling the temperature profile of an amorphous silicon in the laser annealing for crystallizing and activating the amorphous silicon thereby controlling the crystal grain boundaries. According to the invention, variation in the electric property of the diode can be decreased and the yield of the phase-change memory can be improved.Type: ApplicationFiled: January 29, 2009Publication date: July 30, 2009Inventors: Masaharu Kinoshita, Motoyasu Terao, Hideyuki Matsuoka, Yoshitaka Sasago, Yoshinobu Kimura, Akio Shima, Mitsuharu Tai, Norikatsu Takaura