Abstract: A memory cell in a so-called MRAM by utilizing a tunnel magnetic resistance in the prior art has raised problems that a magnetic field to be applied to a TMR element is essentially weak since a word line for write is disposed apart from the TMR element, that a large current is required at the time of a writing operation, and that electric power consumption is large. In order to solve the above-described problems experienced in the prior art, the present invention provides an MRAM memory cell structure and its fabricating method in which a word line for write is disposed near a TMR element and surrounds it in three directions.

Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).

Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: A write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.

Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change recording film contains at least two of Ge, Sb and Te as main constituting elements thereof. The first electrode comprises material of group of Ti, Si and N, or group of Ta, Si and N as main constituting material thereof.

Abstract: In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. At this time, if a constant voltage source is used, not only the phase change portion assumes a state of a low resistance, but also a large current flows, so that a sample concerned is overheated and goes into a state of a high resistance. Thus, it is difficult to make the phase change portion low in resistance stably. When the gate voltage of a memory cell selection transistor QM is controlled with MISFET to afford a low resistance state, the maximum amount of current applied to the sample is limited by the application of a medium-state voltage.

Abstract: A write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.

Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.

Abstract: A magnetic nonvolatile memory cell includes a C-MOSFET, a spin torque magnetization inversion layer and a tunneling magnetoresistive layer arranged in this order. The memory cell has the function of spin torque magnetization inversion and consumes very low power. A random access memory includes a plurality of the memory cells.

Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved. Each gate electrode in a memory cell area is formed of p type polycrystalline silicon, and a cap insulating film on each gate electrode and a sidewall film on the sidewall thereof are formed of a silicon oxide film. A polycrystalline silicon film formed on the gate electrodes and between the gate electrodes is polished by a CMP method, and thereby contact electrodes are formed. Also, sidewall films each composed of a laminated film of the silicon oxide film and the polycrystalline silicon film are formed on the sidewall of the gate electrodes in the logic circuit area, and these films are used as a mask to form semiconductor areas. As a result, it is possible to reduce the boron penetration and form contact electrodes in a self-alignment manner. In addition, the performance of the MISFET constituting the logic circuit can be improved.

Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

Abstract: A manufacturing process for a semiconductor integrated circuit device which prevents occurrence of reaction between metal wiring and a boron-doped silicon plug over it in heat treatment for a MOS transistor to be formed over them and reduces the possibility of rise in contact resistance. Metal boride is formed on an exposed metal surface in the bottom of an opening made in an interlayer insulating film over the metal wiring. In order to facilitate formation of such metal boride, metal oxide remaining on the metal surface is removed with an aqueous ammonia solution. The meal surface is irradiated with high energy ultraviolet light in order to remove organic matter remaining in the opening and facilitate removal of the metal oxide with the aqueous ammonia solution.

Abstract: A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficultly of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.

Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.

Abstract: There is disclosed a write operation of a MRAM in which a current necessary for inverting magnetization of an MTJ element has to be passed through a data line and therefore current consumption is large. The write operation comprises: comparing input data DI with read data GO read from a memory cell array and encoding the input data DI to form write data GI by a data encoder WC; and decoding the read data GO by a data decoder RD to form output data DO. In a nonvolatile semiconductor memory in which the current is passed through the data line to write data into a memory cell, the number of bits to be written during the write operation is reduced, and the current consumption can be reduced. This can realize the MRAM including a low-power highly-integrated memory.

Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.