Abstract: A nonvolatile semiconductor memory device having a large storage capacity and stabilized rewriting conditions in which a memory cell includes a nonvolatile recording material layer, a selector element and a semiconductor layer provided between the nonvolatile recording material layer and the selector element and having a thickness ranging from 5 to 200 nm.

Abstract: A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If a read access occurs to that address before the next write cycle, data is read out from the register without reading the data from the memory cell array. Without elongating the cycle time, it is possible not only to use a long time to write data into a memory cell therein but also to make longer the interval between the time when a write operation is done and the time when the subsequent read operation is made from that memory cell. As a result, data can be written reliably.

Abstract: A phase-change memory device including a memory cell having a memory element and a select transistor is improved in heat resistance so that it may be operable at 145° C. or higher. The memory layer is used which has a content of Zn or Cd of 20 at % or more and 50 at % or less, a content of Ge or Sb of 5 at % or more and 25 at % or less, and a content of Te of 40 at % or more and 65 at % or less in Zn-Ge-Te.

Abstract: A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The phase change recording film contains at least two of Ge, Sb and Te as main constituting elements thereof. The first electrode comprises material of group of Ti, Si and N, or group of Ta, Si and N as main constituting material thereof.

Abstract: In a non-volatile phase change memory, information is recorded by utilizing a change in resistance of a phase change portion. When the phase change portion is allowed to generate Joule's heat and is held at a specific temperature, it goes into a state of a low resistance. When the gate voltage of a memory cell selection transistor QM is controlled to afford a low resistance state, the maximum amount of current applied to the phase change portion is limited by the application of a medium-state voltage to the control gate, thereby avoiding overheating of the phase change portion.

Abstract: A technique that can realize high integration even for multilayered three-dimensional structures at low costs by improving the performance of the semiconductor device having recording or switching functions by employing a device structure that enables high precision controlling of the movement of ions in the solid electrolyte. The semiconductor element of the device is formed as follows; two or more layers are deposited with different components respectively between a pair of electrodes disposed separately in the vertical (z-axis) direction, then a pulse voltage is applied between those electrodes to form a conductive path. The resistance value of the path changes according to an information signal. Furthermore, a region is formed at a middle part of the conductive path. The region is used to accumulate a component that improves the conductivity of the path, thereby enabling the resistance value (rate) to response currently to the information signal.

Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

Abstract: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

Abstract: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

Abstract: A memory device is provided which includes a substrate, lower electrodes, selecting elements, memory elements formed of chalcogenide material and upper electrodes. The selecting elements and the memory elements are arranged to be disposed between the upper electrodes and the lower electrodes. In addition, the lower electrodes, the memory elements and the upper electrodes are disposed along lines perpendicular to the substrate surface when the memory device is viewed in a first direction.

Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected wordline conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.

Abstract: With a high-speed nonvolatile phase change memory, reliability in respect of the number of refresh times is enhanced. In a memory cell forming area of a phase change memory using a MISFET as a transistor for selection of memory cells, a phase change material layer of a memory cell comprising a resistor element, using a phase change material, is formed for common use. As a result, variation in shape and a change in composition of the phase change material, caused by isolation of memory cell elements by etching, are reduced, thereby enhancing reliability of memory cells, in respect of the number of refresh times.

Abstract: A phase change memory device is provided which is constituted by memory cells using memory elements and select transistors and having high heat resistance to be capable of an operation at 140 degrees or higher. As a device configuration, a recording layer of which, of Zn—Ge—Te, content of Zn, Cd or the like is 20 atom percent or more, content of at least one element selected from the group consisting of Ge and Sb is less than 40 atom percent, and content of Te is 40 atom percent or more is used. It is thereby possible to implement the memory device usable for an application which may be performed at a high temperature such as an in-vehicle use.

Abstract: A display arranged with, in a matrix way, signal lines for providing brightness information to each of pixels, and scanning lines for selecting, in a predetermined cycle, pixels to be provided with brightness information; intake of the brightness information to each of the pixels being executed by intake of signal voltage of the signal lines via thin-film transistors in each of said pixels, in selecting the scanning lines connected with each of the pixels; and having pixels of n-lines and m-rows, by which the brightness information taken into each of the pixels is retained by capacity thereof, even after the scanning lines connected with each of the pixels become a non-selection state, wherein each of the pixels of each line is provided with at least one semiconductor layer that is common between each of the pixels, and the semiconductor layer is formed in parallel to said signal lines.

Abstract: The object of the invention is to avoid an unselected data line being driven in a memory array composed of memory cells each of which uses a storage element depending upon variable resistance and a selection transistor when the selection transistors in all memory cells on a selected word line conduct. To achieve the object, a source line parallel to a data line is provided, a precharge circuit for equipotentially driving both and a circuit for selectively driving the source line are arranged. Owing to this configuration, a current path is created in only a cell selected by a row decoder and a column decoder and a read-out signal can be generated. Therefore, a lower-power, lower-noise and more highly integrated nonvolatile memory such as a phase change memory can be realized, compared with a conventional type.

Abstract: A phase-change memory for employing chalcogenide as a recording medium is disclosed, which prevents the read disturbance from being generated, and reads data at high speed. In a phase-change memory cell array including a selection transistor and chalcogenide, a substrate potential of the selection transistor is isolated in a direction perpendicular to the word lines. During the data recording, a forward current signal flows between the substrate and the source line connected to chalcogenide, and the selection transistor is not used. During the data reading, a desired cell is selected by the selection transistor. Therefore, a recording voltage is greatly higher than the reading voltage, such that the occurrence of read disturbance is prevented, and a high-speed operation is implemented.

Abstract: A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).

Abstract: A phase change memory is provided with a write data register, an output data selector, a write address register, an address comparator and a flag register. Write data is not only written into a memory cell but also retained by the write data register until the next write cycle. If a read access occurs to that address before the next write cycle, data is read out from the register without reading the data from the memory cell array. Without elongating the cycle time, it is possible not only to use a long time to write data into a memory cell therein but also to make longer the interval between the time when a write operation is done and the time when the subsequent read operation is made from that memory cell. As a result, data can be written reliably.