Patents by Inventor Hideyuki Matsuoka
Hideyuki Matsuoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040021159Abstract: A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.Type: ApplicationFiled: July 31, 2003Publication date: February 5, 2004Applicant: Hitachi, Ltd.Inventors: Hideyuki Matsuoka, Satoru Yamada, Isamu Asano, Ryo Nagai, Tomonori Sekiguchi, Riichiro Takemura
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Patent number: 6677633Abstract: In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).Type: GrantFiled: April 8, 2003Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka
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Patent number: 6677194Abstract: A low threshold voltage NMIS area and a high threshold voltage PMIS area are set by a photoresist mask also used for well formation. Using a photoresist mask with openings for the NMIS and PMIS, the NMIS and PMIS areas are set by one ion implantation step. After gate oxidation, ion implantation is conducted through an amorphous silicon film onto wells, channels, and gate electrodes. A plurality of CMIS threshold voltages can be set and the gate electrodes of both polarities can be formed in a reduced number of steps using photoresist. This solves the problem in which photomasks are required as many as there are ion implantation types for wells, channel stoppers, gate electrodes, and threshold voltage control and hence the number of manufacturing steps and the production cost are increased.Type: GrantFiled: June 6, 2002Date of Patent: January 13, 2004Assignee: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Akio Nishida, Yasuko Yoshida, Shuji Ikeda, Kenichi Kuroda, Shiro Kamohara, Shinichiro Kimura, Eiichi Murakami, Hideyuki Matsuoka, Masataka Minami
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Publication number: 20040000690Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.Type: ApplicationFiled: January 8, 2003Publication date: January 1, 2004Inventors: Hiroshi Kujirai, Masahiro Moniwa, Kazuo Nakazato, Teruaki Kisu, Teruo Kisu, Hideyuki Matsuoka, Tsuyoshi Tabata
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Patent number: 6670642Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.Type: GrantFiled: January 22, 2002Date of Patent: December 30, 2003Assignee: Renesas Technology Corporation.Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Riichiro Takemura, Kousuke Okuyama, Masahiro Moniwa, Akio Nishida, Kota Funayama, Tomonori Sekiguchi
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Patent number: 6661048Abstract: According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.Type: GrantFiled: April 5, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Toshiaki Yamanaka, Shin′ichiro Kimura, Hideyuki Matsuoka, Tomonori Sekiguchi, Takeshi Sakata, Kiyoo Itoh
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Publication number: 20030173628Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the-amplified current to an associated read data line.Type: ApplicationFiled: April 14, 2003Publication date: September 18, 2003Applicant: Hitachi, Ltd.Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka, Katsuro Watanabe, Kenchi Ito
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Patent number: 6621110Abstract: A DRAM of an open bit line structure has a cell area smaller than that of a DRAM of a folded bit line structure and is susceptible to noise. A conventional DRAM of an open bit line structure has a large bit line capacitance and is susceptible to noise or has a large cell area. There has been no DRAM of an open bit line structure having a small bit line capacitance, unsusceptible to noise and having a small cell area. The present invention forms capacitor lower electrode plug holes not aligned with bit lines to reduce bit line capacitance. Bit lines are formed in a small width, capacitor lower electrode plugs are dislocated from positions corresponding to the centers of the bit lines in directions away from the bit lines and the contacts are formed in a reduced diameter to avoid increasing the cell area. Thus a semiconductor storage device of an open bit line structure resistant to noise and having a small cell area is provided.Type: GrantFiled: June 13, 2000Date of Patent: September 16, 2003Assignee: Hitachi, Ltd.Inventors: Hideyuki Matsuoka, Satoru Yamada, Isamu Asano, Ryo Nagai, Tomonori Sekiguchi, Riichiro Takemura
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Publication number: 20030168685Abstract: In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).Type: ApplicationFiled: April 8, 2003Publication date: September 11, 2003Applicant: Hitachi, Ltd.Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka
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Patent number: 6617205Abstract: A capacitor consisting of a storage electrode (19), a capacitor dielectric film (20) and a plate electrode (21) is formed in a trench formed through dielectric films (6, 8, 10 and 12) stacked on a semiconductor substrate (1) and buried wiring layers (9 and 11) are formed under the capacitor. As the capacitor is formed not in the semiconductor substrate but over it, there is room in area in which the capacitor can be formed and the difficulty of forming wiring is reduced by using the wiring layers (9 and 11) for a global word line and a selector line. As the upper face of an dielectric film (32) which is in contact with the lower face of wiring (34) in a peripheral circuit area is extended into a memory cell area and is in contact with the side of the capacitor (33), step height between the peripheral circuit area and the memory cell area is remarkably reduced.Type: GrantFiled: May 20, 1998Date of Patent: September 9, 2003Assignee: Hitachi, Ltd.Inventors: Shinichiro Kimura, Toshiaki Yamanaka, Kiyoo Itoh, Takeshi Sakata, Tomonori Sekiguchi, Hideyuki Matsuoka
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Publication number: 20030146469Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.Type: ApplicationFiled: December 2, 2002Publication date: August 7, 2003Applicant: Hitachi, Ltd.Inventors: Hideyuki Matsuoka, Kiyoo Itoh, Motoyasu Terao, Satoru Hanzawa, Takeshi Sakata
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Publication number: 20030136978Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.Type: ApplicationFiled: January 22, 2002Publication date: July 24, 2003Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Riichiro Takemura, Kousuke Okuyama, Masahiro Moniwa, Akio Nishida, Kota Funayama, Tomonori Sekiguchi
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Publication number: 20030111707Abstract: A semiconductor integrated circuit device is provided, in which variation in the threshold voltage of a MISFET, for example, a MISFET pair that constitute a sense amplifier, can be reduced. In a logic circuit area over which a logic circuit such as a sense amplifier circuit required to drive a memory cell is formed, n-type active areas having no gate electrode are arranged at both edges of active areas over which a p-channel MISFET pair for constituting a sense amplifier are formed. Assuming that the width between active areas nwp1 and nw1 is L4, the width between active areas nwp2 and nw2 is L6, and the width between active areas nwp1 and nwp2 is L5, (L4-L5), (L6-L5), and (L4-L6) are set equal to almost zero or smaller than twice the minimum processing dimension, so that the variation in shape of the device isolation trenches with the widths L4, L5, and L6 can be reduced, and the threshold voltage difference in the MISFET pair can be reduced.Type: ApplicationFiled: November 19, 2002Publication date: June 19, 2003Applicant: Hitachi, Ltd.Inventors: Norikatsu Takaura, Riichiro Takemura, Hideyuki Matsuoka, Shinichiro Kimura, Hisao Asakura, Ryo Nagai, Satoru Yamada
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Publication number: 20030109102Abstract: A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.Type: ApplicationFiled: October 24, 2002Publication date: June 12, 2003Inventors: Hiroshi Kujirai, Masahiro Moniwa, Kazuo Nakazato, Teruaki Kisu, Teruo Kisu, Teruaki Kisu, Haruko Kisu, Hideyuki Matsuoka, Tsuyoshi Tabata, Satoru Haga
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Patent number: 6576510Abstract: According to the present invention, an overlay margin is secured for matching a wiring electrode 11 with a storage electrode 15 of a capacitor at their point of contact and the required area for a memory cell can be decreased by placing the plug electrode 11 of titanium nitride in the active region of a semiconductor substrate or over the gate electrode, reducing the size of the opening for passing the storage electrode 15 of the capacitor of a stacked structure, and decreasing the line width of a wiring electrode 13. By the common use of the above-mentioned plug electrodes in a CMISFET region in the peripheral circuit and in a memory cell of a static RAM, their circuit layouts can be made compact.Type: GrantFiled: April 5, 2001Date of Patent: June 10, 2003Inventors: Toshiaki Yamanaka, Shin' ichiro Kimura, Hideyuki Matsuoka, Tomonori Sekiguchi, Takeshi Sakata, Kiyoo Itoh
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Patent number: 6573586Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.Type: GrantFiled: February 25, 2002Date of Patent: June 3, 2003Assignee: Hitachi, Ltd.Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka, Katsuro Watanabe, Kenchi Ito
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Patent number: 6570206Abstract: In manufacturing a semiconductor memory by using conventional gain cells, it is difficult to integrate them similarly to 1T1C cells of a DRAM if mask alignment accuracy is considered. In order to achieve integration similarly to that of 1T1C cells by using gain cells, a memory cell block constituted as follows is used. A memory block (MCT) comprises a plurality of memory cells (MC0-MC3). Each memory cell includes a PMOS transistor (M0) for writing and an NMOS transistor (M1) for reading, and information is stored by holding electric charge in a storage node. The write transistors (M0) are arranged in parallel in a plurality of cells, each source-drain path is connected to a data line (DL). The read transistors (M1) are connected in series in a plurality of cells, and are connected to the data line (DL) via a block selection transistor (MB).Type: GrantFiled: September 24, 2002Date of Patent: May 27, 2003Assignee: Hitachi, Ltd.Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka
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Patent number: 6560135Abstract: Since a memory cell of a so-called MRAM utilizing a conventional tunnel magnetic resistance forms writing word lines below data lines, there are the following problems. A process becomes hard because it is necessary to execute a self-aligned contact opening process with passing through portions between the writing word lines, or since it is hard that the writing word lines sufficiently overlap with a magnetic resistance device in a planner manner due to a restriction of layout, the data writing becomes unstable. In order to solve the problems mentioned above, the present invention provides a structure of MRAM memory cell in which the writing word lines are formed above the bit lines, and a method of manufacturing the same.Type: GrantFiled: August 23, 2001Date of Patent: May 6, 2003Assignee: Hitachi, Ltd.Inventors: Hideyuki Matsuoka, Takeshi Sakata, Katsuro Watanabe, Kiyoo Itoh
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Publication number: 20030011002Abstract: A refresh characteristic of a DRAM memory cell is improved and the performance of a MISFET formed in the periphery thereof and constituting a logic circuit is improved.Type: ApplicationFiled: June 7, 2002Publication date: January 16, 2003Applicant: Hitachi, Ltd.Inventors: Norikatsu Takaura, Hideyuki Matsuoka, Shinichiro Kimura, Ryo Nagai, Satoru Yamada
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Publication number: 20020195630Abstract: Disclosed are a fast, highly-integrated and highly-reliable magnetoresistive random access memory (MRAM) and a semiconductor device which uses the MRAM. The semiconductor device performs the read-out operation of the MRAM using memory cells for storing information by using a change in magnetoresistance of a magnetic tunnel junction (MTJ) element with a high S/N ratio. Each memory cell includes an MTJ element and a bipolar transistor. The read-out operation is carried out by selecting a word line, amplifying a current flowing in the MTJ element of a target memory cell by the bipolar transistor and outputting the amplified current to an associated read data line.Type: ApplicationFiled: February 25, 2002Publication date: December 26, 2002Inventors: Takeshi Sakata, Satoru Hanzawa, Hideyuki Matsuoka, Katsuro Watanabe, Kenchi Ito