Abstract: A domino logic circuit having an input terminal and a precharge node. A first switch is responsive to a second switch sensing one of a high or low voltage at the precharge node to charge the precharge node and the second switch is responsive to the one of a high or low voltage at the precharge node to control the first switch charging the precharge node. The first switch is preferably a p-channel transistor and the second switch is preferably an n-channel transistor. The circuit also includes an output terminal, an inverter coupled between the precharge node and the output terminal and feedback circuitry coupled between the output terminal and coupled to the second switch to provide the charge state of the precharge node to the second switch. The circuit further includes a pair of transistors having serially connected current paths, the serially connected current paths being coupled between the precharge node and a reference source.

Abstract: A method of operating a memory circuit having a plurality of blocks of memory cells (400-404) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells (400) is selected in response to a first address signal (RAY0). A row of memory cells (430-436) in the first block of memory cells is selected in response to a second address signal (RAX0). A first voltage is applied to a first power supply terminal (412) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal (412) of another block of memory cells (402) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

Abstract: A method of operating a memory circuit having a plurality of blocks of memory cells (400–404) is disclosed. The method includes storing data in the plurality of blocks of memory cells. A first block of memory cells (400) is selected in response to a first address signal (RAY0). A row of memory cells (430–436) in the first block of memory cells is selected in response to a second address signal (RAX0). A first voltage is applied to a first power supply terminal (412) of the first block of memory cells in response to the first address signal. A second voltage different from the first voltage is applied to a first power supply terminal (412) of another block of memory cells (402) of the plurality of blocks of memory cells. Data is retained in the other block of memory cells.

Abstract: Systems and methods are provided for reducing power consumption in the form of leakage current in a memory array. One embodiment discloses a memory array system. The memory array system comprises a plurality of memory cells and a programmable switching control circuit. The programmable switching control circuit is operative to arrange the plurality of memory cells in a standard configuration in an activation mode and to arrange the plurality of memory cells in a stacked configuration in a retention mode.

Abstract: A charge pump circuit. The circuit includes an input node for receiving a clock signal having cycles. The charge pump circuit includes a pump circuit coupled to the input node, including a first capacitor and having an output node coupled to a second capacitor, the pump circuit operating to provide a predetermined charge the second capacitor in response to a cycle of the clock signal. The predetermined charge corresponds to the amount of charge accumulated on the first capacitor during the cycle of the clock signal.

Abstract: In a transceiver unit including an adaptive equalizer filter unit, apparatus is provided for reducing or compressing the number of bits representing an error signal. The apparatus replaces a plurality of the most significant logic signal bits with a single bits while transferring the sign logic signal bit and the logic signal bits of lesser significance unchanged. Because of the reduction in the number of logic signal bits, the number of components implementing the multiplier unit in the adaptive filter unit can be reduced (i.e., in each stage of the adaptive filter). The reduction of the apparatus implementing the processing the error signal results in the same equilibrium value of the error signal, however, the time to reach this equilibrium value is increased.

Abstract: A circuit for improving the performance of a charging capacitor inverter used in VCO and similar circuits. The disclosed approach is used to provide both trip point and charging current delay control to reduce the amount of “jitter” associated with the circuit. Trip point delay control is accomplished by adding an in-line transistor, output in a typical charged capacitor inverter, between the charging capacitor and the circuit. The threshold of this transistor is controlled by a dc bias level (control voltage) which allows this transistor to turn “ON” or “OFF” when the node voltage of the capacitor reaches the controllable preset level. Further control of the circuit's delay is obtained by means of circuitry which allows the amount of capacitor charging current to be selected.

Abstract: A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output.

Abstract: A data converter (20) comprising an input (I0′-I3′) for receiving a digital word and an output (VOUT2) for providing an analog voltage level in response to the digital word. The data converter further comprises a plurality of bit lines (BL0′-BL3′) formed with an alignment in a first dimension and a plurality of word lines (WL0′-WL4′) formed with an alignment in a second dimension different than the first dimension. Further, the data converter comprises a string (12′) comprising a plurality of series connected resistive elements (R0′-R14′). The string comprises a plurality of voltage taps (T0′-T15′), and at least a majority of the plurality of series connected resistive elements are formed with an alignment in the first dimension. The data converter also comprises a plurality of switching transistors (ST0′-ST15′) coupled between the plurality of voltage taps and the output.

Abstract: In a fast adaptive filter unit, an update unit replaces the multiplier unit which generates a product of the filter constant, the error signal and data signal and adding this product to a previously generated coefficient with a reduced complexity unit. The reduced complexity unit determines the sign of the product and whether the product is zero or non-zero. As a result of this determination a two bit signal is generated which is used to either increment or decrement the count in a register in the counter unit. The count held by the register is the coefficient signal, the coefficient signal being updated by each additional operation. In order to prevent the register from over-flowing, a second counter applies a signal periodically to the counter unit which decrements the magnitude of coefficient signal stored in the register by one count.

Abstract: A stacked cache memory system and method is provided. The stacked cache memory system (10) may include a memory cell array (22) coupled to a cache system (30). The memory cell array (22) stores and retrieves a data signal. Recently retrieved data signals are stored in a number of sense-amp memory cells (52) within the cache system (30). A column select system (32) is coupled to the cache system (30). A logic subsystem (12) controls the column select system (32) such that the column select system (32) directs the data signal from the memory cell array (22) to a sense-amp system (34) or directs a stored data output signal from the cache system (30) to a switching system (36). The sense-amp system (34) senses and amplifies the data signal and produces an amplified data output signal.

Abstract: A stacked sense-amp cache memory system and method is provided. The stacked sense-amp cache memory system (10) may comprise a memory cell array (22) coupled to a cache system (30). The memory cell array (22) stores and retrieves a data signal. Recently retrieved data signals are stored in the cache system (30). A column select system (32) is coupled to the cache system (30). A logic subsystem (12) controls the column select system (32) such that the column select system (32) directs the data signal from the memory cell array (22) to a sense-amp system (34) or directs a stored data output signal from the cache system (30) to a switching system (36). The sense-amp system (34) senses and amplifies the data signal and produces an amplified data output signal. The switching system (36) is coupled to the sense-amp system (34) and the cache system (30) and operates to select between the amplified data output signal from the sense-amp system (34) and the stored data output signal from the cache system (30).

Abstract: A random access memory array architecture including a plurality of arrays or subarrays arranged into rows and columns, a plurality of sense amplifiers between the arrays (2), and grouped input/output (I/O) lines. The I/O path includes main I/O lines (24) coupled to all of the arrays, with orthogonal local I/O lines (20) for a column of arrays plus sub I/O lines (16) orthogonal to the local I/O lines for each group of sense amplifiers in a row of sense amplifiers. A plurality of pass transistor pairs and interconnect transistors are coupled to the sense amplifiers and the local and sub I/O lines. Latches are provided for storing data output from each of the subarrays, and a match comparator is connected to at least two of the latches for providing a signal on a complementary pair of match leads indicative of a comparison of the data in the latches.

Abstract: A memory sensing scheme is disclosed which does not require the use of a dummy cell. The memory sensing scheme uses charge injection and parasitic capacitive coupling to distinguish the logical content of a memory cell.

Abstract: A memory element for a static random access memory which comprises a bit line and a bit line for providing a voltage on one of the lines indicative of a binary "1" or a "0" and the other of a "1" or a "0" on the other line. A sense amplifier is coupled to the bit and bit lines, the sense amplifier including a first switch coupled to the bit line and a second switch coupled to the bit line. The element also includes circuitry associated with the bit line and responsive to a select signal to indicate the voltage level of the bit line and to indicate the voltage level of the bit line. The first and second switches are responsive to the circuitry to turn off one of said first and second switches and turn on the other of said first and second switches when the difference in voltage level on the bit and bit lines is in one direction and to turn off and on the other of the switches when the difference in voltage level on the bit and bit lines is in the opposite direction.

Abstract: A memory array architecture is disclosed which funnels data through a series of sets of input/output data lines. Additionally, the invention allows a variable number of sense amplifiers to be used with a single local differential amplifier, thereby permitting high speed sensing.

Abstract: A high speed signal driving scheme is disclosed which reduces timing delays associated with a signal line precharged to a selected voltage by limiting the voltage transition on the signal line from its precharged voltage.

Abstract: This is a method of testing (burn-in and/or stress test) any portion, preferably all, of a plurality of memory cells and the pass gates of transistors (i.e. item 38 of FIG. 2) connecting the memory cells (i.e. item 40 of FIG. 2) to datalines (i.e. item 26) of a memory device. The method is comprised of: accessing every memory cell of the portion of the plurality of memory cells; supplying, preferably by a source external to or internal to the memory device, a positive voltage, preferably greater than that used during normal usage, to a first electrode (i.e. item 46 of FIG. 2) of every accessed memory cell concurrently with supplying, preferably by a source either external to or internal to the memory device, a lower voltage, preferably around zero volts, to the other electrode (i.e. item 44 of FIG.

Abstract: An address match scheme is disclosed which allows the alternate selection of fuses blown based on either logic ones or logic zeros in an address.

Abstract: A self latching input buffer is disclosed which includes an address input buffer which is responsive to a first clock signal so as to produce an output signal. data in the input buffer is latched in connection with the receipt of a second clock signal which is produced by a detector which is responsive to the output signal.