Abstract: A bipolar-CMOS static random access memory device which includes a plurality of static random access memory cells arranged in columns and rows, complementary pairs of bit lines coupled to the cells in each row, word lines coupled to the cells in each row of the cells and a plurality of sense amplifiers and write circuits, with a separate sense amplifier and write circuit coupled to each pair of the complementary bit lines.

Abstract: A circuit is disclosed for generating a two-stage boot signal, the first stage being a transition from a low voltage to a high voltage, and the second stage being a transition from the high voltage to an increased high voltage. The first stage operates to read the contents from a memory cell, and the second stage operates to restore the contents of the access memory cell. A capacitor (102) is charged with a voltage to boost the output (122) of the circuit (52) in order to produce the increased high voltage. However, the lower plate (100) of the capacitor (102) is effectively disconnected from the circuit during the transition from a low to high voltage in order to provide a fast transition period.

Abstract: A circuit for detecting a short circuit in a SRAM memory cell (10) includes means for connecting the nodes (21, 23) of the memory cell to the gates of a pair of pulldown transistors (66, 68). The pulldown transistors perform a level-shifting function to produce a voltage pattern that has one high node and one low node (72, 74) for a normal cell and two intermediate voltage nodes for a shorted cell. A following logic circuit (76) responds to the voltage pattern to produce an output voltage that has one value when the cell is functioning correctly and another value when the cell is shorted.

Abstract: A CMOS memory arrangement having each of a plurality of data lines connected to a plurality of bitlines, at least one of said datalines having a lesser number of bitlines in order to decrease capacitance in slower signal paths and thereby increase the operating speed of the memory. A multiple input sense amplifier is connected to the plurality of data lines.