Patents by Inventor Hing To

Hing To has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11886931
    Abstract: The technology disclosed relates to inter-node execution of configuration files on reconfigurable processors using network interface controller (NIC) buffers. In particular, the technology disclosed relates to a runtime logic that is configured to execute configuration files that define applications and application data for applications using a first reconfigurable processor connected to a first host, and a second reconfigurable processor connected to a second host. The first reconfigurable processor is configured to push input data for the applications in a first plurality of buffers. The first host is configured to cause a first network interface controller (NIC) to stream the input data to a second plurality of buffers from the first plurality of buffers. The second host is configured to cause a second NIC to stream the input data to the second reconfigurable processor from the second plurality of buffers.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 30, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Patent number: 11886930
    Abstract: The technology disclosed relates to runtime execution of functions across reconfigurable processor. In particular, the technology disclosed relates to a runtime logic that is configured to execute a first set of functions in a plurality of functions and/or data therefor on a first reconfigurable processor, and a second set of functions in the plurality of functions and/or data therefor on additional reconfigurable processors. Functions in the second set of functions and/or the data therefor are transmitted to the additional reconfigurable processors using one or more of a first reconfigurable processor-to-additional reconfigurable processors buffers, and results of executing the functions and/or the data therefor on the additional reconfigurable processors are transmitted to the first reconfigurable processor using one or more of additional reconfigurable processors-to-first reconfigurable processor buffers.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 30, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Ram Sivaramakrishnan, Sumti Jairath, Emre Ali Burhan, Manish K. Shah, Raghu Prabhakar, Ravinder Kumar, Arnav Goel, Ranen Chatterjee, Gregory Frederick Grohoski, Kin Hing Leung, Dawei Huang, Manoj Unnikrishnan, Martin Russell Raumann, Bandish B. Shah
  • Publication number: 20240028192
    Abstract: A method for sharing an image with one or more overlays on a mobile platform includes the steps of receiving an image; adding an overlay to the receive image, the overlay being a generated content conveying an impression when viewing the received image; recognizing by matching the overlay to a set of templates for identifying a template intended of the overlay; assigning the template which is recognized with the overlay to the received image; superimposing the template onto the received image to create a new image, the new image indicating the conveyed impression; and saving the new image into a file, the file including information regarding a review directed to the content displayed in the received image and correlated to the conveyed impression.
    Type: Application
    Filed: September 28, 2023
    Publication date: January 25, 2024
    Inventors: Stephanie Suk Hing CHAN, Johnny Key Jye CHEN
  • Publication number: 20240020170
    Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for estimating a cost of implementing an operation unit graph. The operation unit graph may include first and second logical units that perform first and second data operations and have first and second ports, respectively, coupled by a logical edge, on a reconfigurable processor. The method includes receiving the operation unit graph, determining first and second upper bandwidth limits of the first and second ports, respectively, determining a logical edge bandwidth of the logical edge based on the first and second upper bandwidth limits, determining a timing group for the logical edge, and providing the logical edge bandwidth and the timing group as a cost estimation of implementing the operation unit graph on the reconfigurable processor.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Yue FU, Kin Hing LEUNG, Arvind Krishna SUJEETH, Sumti JAIRATH, Andrew DENG, Chris RÉ, Raghu PRABHAKAR
  • Publication number: 20240020264
    Abstract: A cost estimation tool in a system for implementing an operation unit graph on a reconfigurable processor is presented as well as a method of operating a cost estimation tool for determining scaled logical edge bandwidths in an operation unit graph in preparation of placing and routing the operation unit graph onto a reconfigurable processor. The cost estimation tool may be configured to receive the operation unit graph, divide the operation unit graph in first and second subgraphs, determine maximum latencies of the first and second subgraphs, and determine a scaled logical edge bandwidth of a logical edge that couples a first logical unit of M logical units in the first subgraph with a second logical unit of N logical units in the first subgraph based on M, N, and scaled bandwidth limits of the M and N logical units.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Yue FU, Kin Hing LEUNG, Joshua BROT, Arvind Krishna SUJEETH, Sumti JAIRATH, Andrew DENG, Chris RÉ, Raghu PRABHAKAR
  • Publication number: 20240020265
    Abstract: A system with a cost estimation tool for estimating a realized bandwidth consumption of a logical edge between a logical producer unit and a logical consumer unit of an operation unit graph during placement and routing of the logical producer unit, the logical consumer unit, and the logical edge onto a reconfigurable processor is presented as well as a method of operating such a cost estimation tool and a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate such a cost estimation tool The cost estimation tool may be configured to determine the realized bandwidth consumption of the tentative assignment based on an upper bandwidth limit of the logical edge, an end-to-end bandwidth, a scaling factor of a realized bandwidth, and a congestion estimation of the physical link.
    Type: Application
    Filed: July 13, 2023
    Publication date: January 18, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Yue FU, Kin Hing LEUNG, Likun HAO, Arvind Krishna SUJEETH, Sumti JAIRATH, Andrew DENG, Chris RÉ, Raghu PRABHAKAR
  • Patent number: 11875466
    Abstract: Systems and methods for matching content elements to surfaces in a spatially organized 3D environment. The method includes receiving content, identifying one or more elements in the content, determining one or more surfaces, matching the one or more elements to the one or more surfaces, and displaying the one or more elements as virtual content onto the one or more surfaces.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: January 16, 2024
    Inventors: Denys Bastov, Victor Ng-Thow-Hing, Benjamin Zaaron Reinhardt, Leonid Zolotarev, Yannick Pellet, Aleksei Marchenko, Brian Everett Meaney, Marc Coleman Shelton, Megan Ann Geiman, John A. Gotcher, Matthew Schon Bogue, Shivakumar Balasubramanyam, Jeffrey Edward Ruediger, David Charles Lundmark
  • Patent number: 11872272
    Abstract: The invention features multi-specific fusion protein complexes with one domain comprising IL-15 or a functional variant and a binding domain specific to IL-12 or IL-18.
    Type: Grant
    Filed: February 13, 2023
    Date of Patent: January 16, 2024
    Assignee: Altor Bioscience, LLC
    Inventors: Warren D. Marcus, Robert Newman, Bai Liu, Lijing You, Lin Kong, Peter Rhode, Hing C. Wong
  • Patent number: 11864978
    Abstract: A computer-implemented bone-implant system evaluation method for application of mesh-free analysis of a bone-implant system for evaluation of performance of a bone-implant system for an implant implanted within the bone structure at an anatomical site, said method comprising (i) receiving a set of bone structure data set, wherein set of bone structure data includes data indicative of the bone structure at an anatomical site; (ii) inputting an implant data set and inputting the position of the implant data set, wherein the implant is selected based upon the biomechanical requirements for the anatomical site and the position and of the implant data set is indicative of the position of the implant with respect to the anatomical site, wherein implant data set includes data representative of the geometry and materials properties of the implant; (iii) creating a bone-implant model, wherein said bone implant-model includes a mesh-free model of trabecular bone at the anatomical site wherein the bone-implant model is
    Type: Grant
    Filed: September 7, 2017
    Date of Patent: January 9, 2024
    Assignee: VERSITECH LIMITED
    Inventors: Sloan Austin Kulper, Hing Wan Alfonso Ngan, Xinshuo Christian Fang, Margaret Guo, Weijia William Lu, Ka Li Frankie Leung
  • Patent number: 11868979
    Abstract: A platform and process for electronic payment processing using electronic communications from different communication channels or bands. The system and process can generate alerts using fraud detection and verify payment requests using historical data and pattern recognition. The system and process can categorize images and extract payment data.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: January 9, 2024
    Assignee: BANK OF MONTREAL
    Inventors: Brian Chan, Kashif Arshad, Peter Hing-Cheong Poon, Vikram Pal
  • Publication number: 20240006533
    Abstract: Contacts to p-type source/drain regions comprise a boride, indium, or gallium metal compound layer. The boride, indium, or gallium metal compound layers can aid in forming thermally stable low resistance contacts. A boride, indium, or gallium metal compound layer is positioned between the source/drain region and the contact metal layer. A boride, indium, or gallium metal compound layer can be used in contacts contacting p-type source/drain regions comprising boron, indium, or gallium as the primary dopant, respectively. The boride, indium, or gallium metal compound layers prevent diffusion of boron, indium, or gallium from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.
    Type: Application
    Filed: July 2, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Siddharth Chouksey, Nazila Haratipour, Christopher Jezewski, Jitendra Kumar Jha, Ilya V. Karpov, Matthew V. Metz, Arnab Sen Gupta, I-Cheng Tung, Nancy Zelick, Chi-Hing Choi, Dan S. Lavric
  • Publication number: 20240006494
    Abstract: Semiconductor structures having a source and/or drain with a refractory metal cap, and methods of forming the same, are described herein. In one example, a semiconductor structure includes a channel, a gate, a source, and a drain. The source and drain contain silicon and germanium, and one or both of the source and drain are capped with a semiconductor cap and a refractory metal cap. The semiconductor cap is on the source and/or drain and contains germanium and boron. The refractory metal cap is on the semiconductor cap and contains a refractory metal.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
  • Publication number: 20240006506
    Abstract: Contacts to n-type source/drain regions comprise a phosphide or arsenide metal compound layer. The phosphide or arsenide metal compound layers can aid in forming thermally stable low resistance contacts. A phosphide or arsenide metal compound layer is positioned between the source/drain region and the contact metal layer of the contact. A phosphide or arsenic metal compound layer can be used in contacts contacting n-type source/drain regions comprising phosphorous or arsenic as the primary dopant, respectively. The phosphide or arsenide metal compound layers prevent diffusion of phosphorous or arsenic from the source/drain region into the metal contact layer and dopant deactivation in the source/drain region due to annealing and other high-temperature processing steps that occur after contact formation.
    Type: Application
    Filed: July 2, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Gilbert Dewey, Siddharth Chouksey, Nazila Haratipour, Christopher Jezewski, Jitendra Kumar Jha, Ilya V. Karpov, Jack T. Kavalieros, Arnab Sen Gupta, I-Cheng Tung, Nancy Zelick, Chi-Hing Choi, Dan S. Lavric
  • Publication number: 20240006488
    Abstract: In one embodiment, layers comprising Carbon (e.g., Silicon Carbide) are on source/drain regions of a transistor, e.g., before gate formation and metallization, and the layers comprising Carbon are later removed in the manufacturing process to form electrical contacts on the source/drain regions.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Nazila Haratipour, Gilbert Dewey, Nancy Zelick, Siddharth Chouksey, I-Cheng Tung, Arnab Sen Gupta, Jitendra Kumar Jha, David Kohen, Natalie Briggs, Chi-Hing Choi, Matthew V. Metz, Jack T. Kavalieros
  • Patent number: 11858153
    Abstract: A spacing comb for a hair cutting appliance. The comb includes a support frame, a series of comb teeth each having a frontal portion and a rear portion, wherein the comb teeth extend from the support frame. The support frame includes a frontal connector bar and a rear connector plate, wherein the frontal portions of the comb teeth extend from the frontal connector bar. The frontal connector bar is inwardly curved towards the rear connector plate, such that a central portion of the frontal connector bar is rearwardly offset from lateral portions thereof. Also described herein is a hair cutting appliance that is equipped with such a spacing comb.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: January 2, 2024
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Luca Iaccarino, Theunis Quaak, Kam Hing Yau, Rob Roetert, Alwin William De Vries
  • Patent number: 11860939
    Abstract: Embodiments of the disclosure provide methods, systems, computer program products for manipulating a table with an XML column in database. According to the method, a SQL statement for a table is received first, wherein the table comprises an XML column which is a representation of a plurality of logical columns of the table, there is at least one XML element in at least one row and in the XML column of the table, and each of the at least one XML element corresponds to a non-null value in a specific row and in a logical column of the plurality of logical columns of the table. Then the SQL statement is parsed. And then the SQL statement is transformed into a hybrid statement being able to process the XML column in response to the parsing result indicating that the SQL statement relates to at least one logical column of the plurality of logical columns. At last the hybrid statement is executed.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: January 2, 2024
    Assignee: International Business Machines Corporation
    Inventors: Xin Peng Liu, Shuo Li, Xiaobo Wang, ShengYan Sun, Kwai Hing Man
  • Publication number: 20230420456
    Abstract: Integrated circuit structures having source or drain structures with low resistivity are described. In an example, integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. Each epitaxial structure of the first and second source or drain structures include silicon, germanium, gallium and boron. The first and second source or drain structures have a resistivity less than 2E-9 Ohm cm2.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Debaleena NANDI, Imola ZIGONEANU, Gilbert DEWEY, Anant H. JAHAGIRDAR, Harold W. KENNEL, Pratik PATEL, Anand S. MURTHY, Chi-Hing CHOI, Mauro J. KOBRINSKY, Tahir GHANI
  • Publication number: 20230419119
    Abstract: Methods, systems, and apparatuses include determining a set of data. The set of data includes multiple numerical ranges associated with an embedding and an attribute. The numerical range is sampled to obtain a sample value which is also associated with the embedding and the attribute. A set of sample value training data is generated, the set including the sample value, the associated embedding, and the associated attribute. A trained neural network prediction model is generated by applying a prediction model to the set of sample value training data. A set of input data is applied to the trained neural network prediction model. An output is determined by the trained neural network prediction model based on the set of input data. The output is a predicted range of values based on an output mean and an output standard deviation.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 28, 2023
    Inventors: Gopiram Roshan Lal, Girish Kathalagiri, Alice Hing-Yee Leung, Daqian Sun, Aman Grover
  • Publication number: 20230420516
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a plurality of nanostructures vertically stacked and separated from one another, a source/drain feature adjacent to the plurality of nanostructures, and an inner spacer layer. The inner spacer layer includes a vertical portion interposing between the plurality of nanostructures and the source/drain feature and a plurality of horizontal portions interposing between the nanostructures. A source/drain junction is located in the vertical portion of the inner spacer layer and is spaced apart from the plurality of nanostructures by a distance.
    Type: Application
    Filed: September 11, 2023
    Publication date: December 28, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Ka-Hing FUNG
  • Patent number: 11854152
    Abstract: Wearable systems for privacy preserving expression generation for augmented or virtual reality client applications. An example method includes receiving, by an expression manager configured to communicate expression information to client applications, a request from a client application for access to the expression information. The expression information reflects information derived from one or more sensors of the wearable system, with the client application being configured to present virtual content including an avatar rendered based on the expression information. A user interface is output for presentation which requests user authorization for the client application to access the expression information. In response to receiving user input indicating user authorization, enabling access to the expression information is enabled. The client application obtains periodic updates to the expression information, and the avatar is rendered based on the periodic updates.
    Type: Grant
    Filed: January 30, 2023
    Date of Patent: December 26, 2023
    Assignee: Magic Leap, Inc.
    Inventors: Tomislav Pejsa, Dushan Vasilevski, Victor Ng-Thow-Hing, Koichi Mori