Abstract: An embodiment method includes: forming a dielectric-containing substrate over a semiconductor substrate; forming a stack of first semiconductor layers and second semiconductor layers over the dielectric-containing substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with one another within the stack; patterning the first semiconductor layer and the second semiconductor layers into a fin structure such that the fin structure includes sacrificial layers including the second semiconductor layers and channel layers including the first semiconductor layers; forming source/drain features adjacent to the sacrificial layers and the channel layers; removing the sacrificial layers of the fin structure so that the channel layers of the fin structure are exposed; and forming a gate structure around the exposed channel layers, wherein the dielectric-containing substrate is interposed between the gate structure and the semiconductor substra

Abstract: A method and system for activity classification. A pressure sensor receives input data resulting from physical activity of a subject performing an activity. The input data includes pressure data from at least one pressure sensor, and may include other data acquired through other types of sensors. A deep learning neural network is applied to the input data for identifying the activity. The neural network is trained with reference to training data from a training database. The training data may include empirical data from a database of previous data of corresponding activities, synthesized data prepared from the empirical data or simulated data. The training data may include data from physical activity of the subject being monitored by the system. Different aspects of the neural network may be trained with reference to the training data, and some aspects may be locked or opened depending on the application and the circumstances.

Abstract: The present invention features compositions and methods featuring ALT-803, a complex of an interleukin-15 (IL-15) superagonist mutant and a dimeric IL-15 receptor ?/Fc fusion protein useful for enhancing an immune response against a neoplasia (e.g., multiple myeloma, melanoma, lymphoma) or a viral infection (e.g., human immunodeficiency virus).

Abstract: A system for executing a graph partitioned across a plurality of reconfigurable computing units includes a processing node that has a first computing unit reconfigurable at a first level of configuration granularity and a second computing unit reconfigurable at a second, finer, level of configuration granularity. The first computing unit is configured by a host system to execute a first dataflow segment of the graph using one or more dataflow pipelines to generate a first intermediate result and to provide the first intermediate result to the second computing unit without passing through the host system. The second computing unit is configured by the host system to execute a second dataflow segment of the graph, dependent upon the first intermediate result, to generate a second intermediate result and to send the second intermediate result to a third computing unit, without passing through the host system, to continue execution of the graph.

Abstract: This present disclosure relates to a flexible heating device having a unique layered assembly structure including a flexible heat generating layer. The present disclosure also relates to a method of manufacturing the flexible heating device and method of use of the flexible heating device in various applications.

Abstract: The present disclosure relates to the field of biotechnology, and more specifically, to single-chain and multi-chain chimeric polypeptides having a linker domain positioned between two target-binding domains that are useful for a variety of applications including, without limitation, stimulating an immune cell, inducing or increasing proliferation of an immune cell, inducing differentiation of an immune cell, or treating a subject in need thereof (e.g., a subject having cancer or an aging-related disease or condition).

Abstract: An electronic package and a method for manufacturing the same is provided. The electronic package includes a first substrate, an electronic component arranged on and/or formed in the first substrate, a thermally conductive second substrate including a first portion and a second portion integrally connected to the first portion, and at least the first portion among the first and second portion is fixedly attached to the electronic component, and a package material arranged to encapsulate the electronic component and to at least partially encapsulate the first and second substrate, and the package material includes a recess formed therein that extends up to a surface of the first portion.

Abstract: A method for performing data recovering operation by an electronic device is provided. The method includes: receiving, by a processor of the electronic device, object data, wherein the object data comprises an incomplete matrix; identifying, by the processor, a plurality of first entries (xi,j) of the incomplete matrix according to the object data; inputting, by the processor, the first entries (xi,j) and a preset maximum loop count (Kmax) into an executed analysis model using Bi-Branch Neural Network (BiBNN) Algorithm; and obtaining, by the processor, a plurality of second entries (mi,j) of a recovered complete matrix corresponding to the incomplete matrix from the analysis model, wherein values of the second entries are determined as original values of the first entries of the incomplete matrix, such that incorrect data in the incomplete matrix is recovered.

Abstract: A reconfigurable processor comprises an array of processing units and an instrumentation network. The array of processing units is configured to execute runtime events to execute an application. The instrumentation network is operatively coupled to the array of processing units. The instrumentation network comprises a control bus configured to form control signal routes in the instrumentation network. The instrumentation network further comprises a plurality of instrumentation counters having inputs and outputs connected to the control bus and to the processing units. Instrumentation counters in the plurality instrumentation units are configurable to consume control signals on the inputs and produce counts of the runtime events on the outputs.

Abstract: Semiconductor devices and methods are provided. In an embodiment, a method includes providing a workpiece including a first hard mask layer on a top surface of a substrate, performing an ion implantation process to form a doped region in the substrate, after the performing of the ion implantation process, annealing the workpiece at temperature T1. The method also includes selectively removing the first hard mask layer, after the selectively removing of the first hard mask layer, performing a pre-bake process at temperature T2, and, after the performing of the pre-bake process, epitaxially growing a vertical stack of alternating channel layers and sacrificial layers on the substrate, where the temperature T2 is lower than the temperature T1.

Abstract: A computing system includes an array of configurable units made up of sub-arrays of configurable units. Each sub-array has a first number of configurable compute units and a second number of configurable memory units with a first spatial arrangement. Each configurable unit includes a configuration data store. The system also includes a statically configurable bus system coupled to the configurable units and a tag indicating a sub-array of configurable units having a defect. A defect-aware configuration controller sends configuration data to the configuration data stores to implement a data processing operation using the array of configurable units by generating static route control signals for the statically configurable bus system, based on the tag and without support of a host processor, to send a portion of the configuration data targeted to the sub-array having the defect to a configuration data store of an alternative sub-array of configurable units in the array.

Abstract: The subject invention pertains to systems and methods for controlling an end-effector moving in three-dimensional space within long piles or shafts. Systems can include a fixed base platform, a cable-driven working platform, a cable-driven end-effector, a sensing system including draw wire sensors, gyroscopes, sonar sensors, and lidar, a control system in communication with the sensing system, and actuators for cables. The end-effector can be configurable to become a cable-driven parallel end-effector, a serially linked arm, a flexible end-effector or an air-lifting end-tool in cases of cleaning founding layers in bored pile shafts. The control system can be configurable to regulate the lengths of cables through actuators and modulate the positions and orientations of the working platform and the end-effector.

Abstract: The present disclosure relates to methods that include the use of a first multi-chain chimeric polypeptide and a second multi-chain chimeric polypeptide for stimulating the NK cells, inducing or increasing proliferation of the NK cells, inducing differentiation of the NK cells, and treating a subject in need thereof using activated NK cells.

Abstract: Provided herein are multi-chain chimeric polypeptides and use thereof in reducing neuroinflammation in a subject.

Abstract: Provided herein are methods of treating an aging-related disease or condition in a subject in need thereof, killing or reducing the number of senescent cells in a subject in need thereof, improving the texture and/or appearance of skin and/or hair in a subject in need thereof, and assisting in the treatment of obesity in a subject in need thereof, that include administering to the subject a therapeutically effective amount of one or more natural killer (NK) cell activating agent(s) and/or a therapeutically effective number of activated NK cells.

Abstract: Semiconductor structures and methods for manufacturing the same are provided. A semiconductor device structure is provided. The semiconductor structure includes a plurality of first nanostructures formed over a substrate, and a gate structure formed over the first nanostructures. The semiconductor structure includes a source/drain (S/D) structure formed adjacent to the gate structure, and a silicide layer formed on a sidewall surface of the S/D structure. The semiconductor structure also includes an S/D contact structure formed over the silicide layer, and the S/D contact structure extends from a first position to a second position The first position is higher than the top surface of the gate structure, and the second position is below the bottommost nanostructure.

Abstract: A method includes forming a gate stack over a fin of a substrate; sequentially depositing a first dielectric layer, a second dielectric layer, a third dielectric layer, and a filling dielectric over the gate stack, wherein the second dielectric layer has a lower dielectric constant than dielectric constants of the first and third dielectric layers; forming a dielectric cap over the first, second, third dielectric layers and the filling dielectric; etching the dielectric cap, the first, second, third dielectric layers, and the filling dielectric simultaneously, to form gate spacers on opposite sidewalls of the gate stack and expose a top surface of the fin; and after the gate spacers are formed, forming an epitaxy source/drain structure in contact with one of the gate spacers and the top surface of the fin.

Abstract: A magnetically actuated pump for pumping liquids in microfluidic devices including one or more substrates and a first flexible membrane arranged to form a pumping chamber having an initial size and volume one or more ports into the pumping chamber.

Abstract: A force sensor for determining a bonding force during wire bonding operations includes: a piezoelectric sensing element mounted in an ultrasonic transducer of an ultrasonic wire bonding device, the piezoelectric sensing element including a first portion and a second portion, and first and second opposing surfaces, wherein the first surface of the first portion has a positive electrode and the second surface of the first portion has a negative electrode respectively, and the first surface of the second portion has a negative electrode and the second surface of the second portion has a positive electrode respectively.