Abstract: In a multilevel interconnection structure for a semiconductor device, lower level interconnections 3 are formed on an insulator film 2 formed on a substrate 1, and a silicon oxide film 4a is formed to cover the lower level interconnections 3 and to fill up a region between adjacent lower level interconnections 3, by means of a biased ECR-CVD process so that a cavity 5 is formed in the silicon oxide film 4a between the adjacent lower level interconnections 3. The silicon oxide film 4a is selectively removed from a tolerable region covering the extent in which a hole for the metal pillar 6 is allowed to deviate from a target lower level interconnection 3, and then, another silicon oxide 4b is formed to fill up the removed portion and to cover the first silicon oxide film. The metal pillar 6 is formed to extend through the silicon oxide film 4b filling the removed portion of the silicon oxide film 4a, so as to reach the target lower level interconnection 3.

Abstract: A base insulator film comprised of a silicon oxide film or the like is formed on the surface of a silicon substrate, and a non-doped polysilicon film (resistor layer) is selectively formed on the base insulator film by thermal CVD. A first silicon oxide film and a BPSG film are sequentially formed on the entire surfaces of the base insulator film and the polysilicon film. Then, two openings which reach the polysilicon film are formed in the BPSG film and the first silicon oxide film, and an impurity is selectively doped into the surface of the polysilicon film through those openings. As a result, a high-resistance section is formed in the polysilicon film between the two openings. Then, the openings are filled with metal layers, and then metal wires to be connected to the metal layers are formed on the surface of the BPSG film.

Abstract: In a method of manufacturing a semiconductor device having a multilayer interconnection structure, when a silicon oxide film is formed onto an electric wiring on a semiconductor substrate by the use of plasma deposition, a first high frequency wave of a constant value is provided for producing plasma while a second high frequency wave of a pulsed amplitude having a predetermined pulse interval and a predetermined rest interval is supplied onto said semiconductor substrate. Silane gas, oxygen gas and argon gas are employed as deposition gases, wherein the argon gas is periodically supplied during a pulsed interval.

Abstract: A planarization method comprises forming on an uneven surface an silicon oxide film having a low wettingness at least on its surface. The low wettingness of the silicon oxide film is obtained by increasing the silicon/oxygen atom ratio by means of argon sputtering or plasma CVD method. A silica solution is subsequently spin-coated onto the silicon oxide film. Since the surface of the silicon oxide film has a low wettingness, more of the coated silica solution stands on recessed portions than on raised portions, resulting in a flat surface of the coated solution. After the coated silica solution has been hardened, etching-back can be carried out until the coated silica solution is completely removed, thereby achieving the planarized surface of the silicon oxide film.

Abstract: The invention provides a method and an apparatus for fabricating a semiconductor device having a silicon oxynitride layer deposited on a semiconductor substrate by means of plasma-enhanced chemical vapor deposition with radio-frequency field being applied to the semiconductor substrate. The method and apparatus use a silane gas, an argon gas and a nitrogen gas as process gases on condition that a flow rate ratio of the argon gas to the silane and nitrogen gases is in the range of at least 1.1, and preferably 2.0 or less. The method and apparatus preferably further use an oxygen gas on condition that a flow rate ratio of the nitrogen gas to the oxygen and nitrogen gases is in the range of at least 0.25, and preferably 0.6 or less. By controlling flow rate ratios of the above mentioned gases in the above mentioned range, the invention provides a silicon oxynitride layer having enhanced burying characteristic and water-permeability resistance and also having smaller dielectric constant and layer stress.