Patents by Inventor Hiroaki Ebihara

Hiroaki Ebihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250240550
    Abstract: A local ramp buffer includes a deep N? well layer disposed in a P? substrate beneath a surface of the P? substrate, a P? well disposed between the surface of the P? substrate and the deep N? well layer, and an N? well structure disposed in the P? substrate and coupled to the deep N? well layer. The N? well structure is disposed between the surface of the P? substrate and the deep N? well layer. The P? well is disposed inside an opening in the N? well structure. The N? well structure and the deep N? well layer are configured to isolate the P? well within the opening. A source follower transistor is disposed in the P? well. The source follower transistor includes a gate terminal coupled to the N? well structure and a ramp generator.
    Type: Application
    Filed: April 10, 2025
    Publication date: July 24, 2025
    Inventors: Shan Chen, Hiroaki Ebihara, Rui Wang, Zhenfu Tian
  • Publication number: 20250211878
    Abstract: A pixel circuit, including a pixel array comprising a plurality of pixels, a plurality of analog to digital converters (ADCs), where during a pixel data readout the plurality of ADCs is communicatively coupled to a respective pixel of the plurality of pixels to receive image data from the respective pixel of the plurality of pixels, a plurality of judge blocks, wherein each judge block is communicatively coupled to a respective ADC of the plurality of ADCs and wherein each judge block is configured to select and transmit gain data based on comparing an output of the respective ADC to a predetermined threshold for the respective ADC, and an image signal processor (ISP) configured to receive outputs from the plurality of ADCs, and combine the outputs of the plurality of ADCs to produce a combined converted value for the respective pixel.
    Type: Application
    Filed: December 22, 2023
    Publication date: June 26, 2025
    Inventors: Nobuhiro Yanagisawa, Hiroaki Ebihara, Hiroki Ui, Naoki Kitazawa, Ryuichi Moriizumi
  • Publication number: 20250193538
    Abstract: A pixel circuit includes a pixel array and a color filter. The pixel array includes pixels arranged in rows and columns, and each pixel includes a photodiode configured to photogenerate image charge in response to incident light, and a transfer transistor coupled to the photodiode to transfer the image charge out from the photodiode. The color filter array includes color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the pixels is coupled to a first readout circuit, and the plurality of pixels includes a first subset of the pixels not coupled to a second readout circuit and a second subset of the pixels coupled to the second readout circuit. Two diagonally arranged pixels are coupled together to share a floating diffusion, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.
    Type: Application
    Filed: October 17, 2024
    Publication date: June 12, 2025
    Inventors: Andreas Suess, Sangjoo Lee, Rui Wang, Hiroaki Ebihara, Eiichi Funatsu
  • Publication number: 20250193555
    Abstract: A pixel circuit includes a pixel array and a color filter. The pixel array includes a plurality of pixels arranged in rows and columns, each pixel including four photodiodes, a floating diffusion, and four transfer transistors. The color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the plurality of pixels is coupled to a first readout circuit, and the plurality of pixels includes (i) a first subset of the pixels not coupled to a second readout circuit and (ii) a second subset of the pixels coupled to the second readout circuit. Floating diffusions of two diagonally arranged pixels are coupled together, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.
    Type: Application
    Filed: October 17, 2024
    Publication date: June 12, 2025
    Inventors: Andreas Suess, Sangjoo Lee, Rui Wang, Hiroaki Ebihara, Eiichi Funatsu
  • Patent number: 12302025
    Abstract: A local ramp buffer includes a deep N? well layer disposed in a P? substrate beneath a surface of the P? substrate, a P? well disposed between the surface of the P? substrate and the deep N? well layer, and an N? well structure disposed in the P? substrate and coupled to the deep N? well layer. The N? well structure is disposed between the surface of the P? substrate and the deep N? well layer. The P? well is disposed inside an opening in the N? well structure. The N? well structure and the deep N? well layer are configured to isolate the P? well within the opening. A source follower transistor is disposed in the P? well. The source follower transistor includes a gate terminal coupled to the N? well structure and a ramp generator.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: May 13, 2025
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Shan Chen, Hiroaki Ebihara, Rui Wang, Zhenfu Tian
  • Patent number: 12294804
    Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: May 6, 2025
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Jiayu Guo, Hiroaki Ebihara, Liang Zuo, Lihang Fan, Satoshi Sakurai
  • Patent number: 12249999
    Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: March 11, 2025
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Rui Wang, Hiroaki Ebihara
  • Publication number: 20250048002
    Abstract: An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: Hiroaki Ebihara, Nobuhiro Yanagisawa, Satoshi Sakurai, Tomoyasu Tate, Naoki Kitazawa, Kohei Harada
  • Publication number: 20250047995
    Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 6, 2025
    Inventors: Liang Zuo, Hiroaki Ebihara, Jing Jun Yi, Rui Wang, Satoshi Sakurai
  • Patent number: 12199632
    Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.
    Type: Grant
    Filed: February 28, 2023
    Date of Patent: January 14, 2025
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Hiroaki Ebihara, Chengcheng Xu, Satoshi Sakurai, Kenny Geng
  • Patent number: 12200389
    Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: January 14, 2025
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Hiroaki Ebihara, Jiayu Guo, Liang Zuo, Lihang Fan
  • Publication number: 20240397226
    Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Inventors: Jiayu Guo, Hiroaki Ebihara, Liang Zuo, Lihang Fan, Satoshi Sakurai
  • Publication number: 20240397236
    Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.
    Type: Application
    Filed: May 23, 2023
    Publication date: November 28, 2024
    Inventors: Hiroaki Ebihara, Jiayu Guo, Liang Zuo, Lihang Fan
  • Patent number: 12114092
    Abstract: A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
    Type: Grant
    Filed: February 17, 2023
    Date of Patent: October 8, 2024
    Assignee: OMNIVISION TECHNOLOGIES, INC.
    Inventors: Rui Wang, Hiroaki Ebihara
  • Publication number: 20240314460
    Abstract: A pixel includes a photosensor configured to photogenerate charge in response to incident light. A floating diffusion is configured to receive the charge photogenerated by the photosensor. A transfer transistor is coupled between the floating diffusion and the photosensor. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A binning node is coupled to the DFD transistor. A floating diffusion interconnect grid is coupled to the binning node of the pixel and a binning node of a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the binning node to the floating diffusion when activated during a readout operation of the pixel array to provide a binned readout, and the DFD transistor is configured not to couple the binning node to the floating diffusion when deactivated to provide a full resolution readout.
    Type: Application
    Filed: December 21, 2023
    Publication date: September 19, 2024
    Inventors: Amit Mittra, Kevin Johnson, Hiroaki Ebihara, Kenny Geng
  • Patent number: 12088937
    Abstract: An imaging device includes a pixel array of pixel circuits arranged in rows and columns. Bitlines are coupled to the pixel circuits. Clamp circuits are coupled to the bitlines. Each of the clamp circuits includes a clamp short transistor to a power line and a respective one of the bitlines. The clamp short transistor is configured to be switched in response to a clamp short enable signal. A first diode drop device is coupled to the power line. A clamp idle transistor is coupled to the first diode drop device such that the first diode drop device and the clamp idle transistor are coupled between the power line and the respective one of the bitlines. The clamp idle transistor is configured to be switched in response to a clamp idle enable signal.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: September 10, 2024
    Assignee: OmniVision Technologies, Inc.
    Inventors: Xuelian Liu, Min Qu, Liang Zuo, Selcuk Sen, Hiroaki Ebihara, Rui Wang, Lihang Fan
  • Publication number: 20240291499
    Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.
    Type: Application
    Filed: February 28, 2023
    Publication date: August 29, 2024
    Inventors: Hiroaki Ebihara, Chengcheng Xu, Satoshi Sakurai, Kenny Geng
  • Publication number: 20240283460
    Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Inventors: Rui Wang, Hiroaki Ebihara
  • Publication number: 20240284074
    Abstract: A pixel cell readout circuit comprises a comparator with a current mirror having first and second current paths, a first input transistor coupled to the first current path, a low conversion gain (LCG) second input transistor selectively coupled to the second current path, and a high conversion gain (HCG) second input transistor selectively coupled to the second current path. The pixel cell readout circuit further comprises a gain network coupled between a gate node of the first input transistor and a ramp generator output, wherein the gain network is configured to provide a variable comparator gain to the comparator, an LCG auto-zero switch coupled between a drain node and a gate node of the LCG second input transistor, and an HCG auto-zero switch coupled between a drain node and a gate node of the HCG second input transistor.
    Type: Application
    Filed: February 17, 2023
    Publication date: August 22, 2024
    Inventors: Rui Wang, Hiroaki Ebihara
  • Publication number: 20240276124
    Abstract: A local ramp buffer includes a deep N? well layer disposed in a P? substrate beneath a surface of the P? substrate, a P? well disposed between the surface of the P? substrate and the deep N? well layer, and an N? well structure disposed in the P? substrate and coupled to the deep N? well layer. The N? well structure is disposed between the surface of the P? substrate and the deep N? well layer. The P? well is disposed inside an opening in the N? well structure. The N? well structure and the deep N? well layer are configured to isolate the P? well within the opening. A source follower transistor is disposed in the P? well. The source follower transistor includes a gate terminal coupled to the N? well structure and a ramp generator.
    Type: Application
    Filed: February 10, 2023
    Publication date: August 15, 2024
    Inventors: Shan Chen, Hiroaki Ebihara, Rui Wang, Zhenfu Tian