Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

Abstract: An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

Abstract: Column amplifiers to support dual conversion gain readout and dual analog gain readout are disclosed herein. In some embodiments, a column amplifier for use in an image sensor can include an input node, and output node, and an input stage coupled between the input node and the output node. The input node can be coupled to receive image signals from one or more pixel circuits. The input stage can include a capacitor array comprising a first capacitor coupled to the input node, a floating voltage node coupled to the first capacitor, and a second capacitor coupled between the floating voltage node and the output node. The input stage can also include a reset switch coupled between the floating voltage node and the output node, and a transistor having a gate terminal coupled to the floating voltage node, and coupled between the output node and ground.

Abstract: An analog-to-digital converter (ADC) converts analog image signal received from a bitline to a digital signal through an ADC comparator. The ADC comparator compares an image signal voltage at its first input against a ramp voltage at its second input to trigger a latch and to cause a digital signal output from the ADC. Each pixel voltage is coupled to only one comparator at its first input through a sample capacitor. A ramp generator generates a global ramp voltage as an input to a plurality of presettable ramp drivers. Each presettable ramp driver outputs a buffered ramp voltage to drive multiple ADC comparators simultaneously at their second inputs. Model circuits of the presettable ramp drivers are disclosed, and respective procedures of presetting the presettable ramp drivers are presented to demonstrate how each of featured presettable ramp drivers is conditioned to drive multiple ADC comparators of the ADCs.

Abstract: An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

Abstract: A pixel includes a photosensor configured to photogenerate charge in response to incident light. A floating diffusion is configured to receive the charge photogenerated by the photosensor. A transfer transistor is coupled between the floating diffusion and the photosensor. A dual floating diffusion (DFD) transistor is coupled to the floating diffusion. A binning node is coupled to the DFD transistor. A floating diffusion interconnect grid is coupled to the binning node of the pixel and a binning node of a second pixel. The pixel and the second pixel are included in a pixel array. The DFD transistor is configured to couple the binning node to the floating diffusion when activated during a readout operation of the pixel array to provide a binned readout, and the DFD transistor is configured not to couple the binning node to the floating diffusion when deactivated to provide a full resolution readout.

Abstract: A pixel circuit, including a pixel array comprising a plurality of pixels, a plurality of analog to digital converters (ADCs), where during a pixel data readout the plurality of ADCs is communicatively coupled to a respective pixel of the plurality of pixels to receive image data from the respective pixel of the plurality of pixels, a plurality of judge blocks, wherein each judge block is communicatively coupled to a respective ADC of the plurality of ADCs and wherein each judge block is configured to select and transmit gain data based on comparing an output of the respective ADC to a predetermined threshold for the respective ADC, and an image signal processor (ISP) configured to receive outputs from the plurality of ADCs, and combine the outputs of the plurality of ADCs to produce a combined converted value for the respective pixel.

Abstract: A local ramp buffer includes a deep N? well layer disposed in a P? substrate beneath a surface of the P? substrate, a P? well disposed between the surface of the P? substrate and the deep N? well layer, and an N? well structure disposed in the P? substrate and coupled to the deep N? well layer. The N? well structure is disposed between the surface of the P? substrate and the deep N? well layer. The P? well is disposed inside an opening in the N? well structure. The N? well structure and the deep N? well layer are configured to isolate the P? well within the opening. A source follower transistor is disposed in the P? well. The source follower transistor includes a gate terminal coupled to the N? well structure and a ramp generator.

Abstract: A pixel circuit, including a pixel array comprising a plurality of pixels, a plurality of analog to digital converters (ADCs), where during a pixel data readout the plurality of ADCs is communicatively coupled to a respective pixel of the plurality of pixels to receive image data from the respective pixel of the plurality of pixels, a plurality of judge blocks, wherein each judge block is communicatively coupled to a respective ADC of the plurality of ADCs and wherein each judge block is configured to select and transmit gain data based on comparing an output of the respective ADC to a predetermined threshold for the respective ADC, and an image signal processor (ISP) configured to receive outputs from the plurality of ADCs, and combine the outputs of the plurality of ADCs to produce a combined converted value for the respective pixel.

Abstract: A pixel circuit includes a pixel array and a color filter. The pixel array includes pixels arranged in rows and columns, and each pixel includes a photodiode configured to photogenerate image charge in response to incident light, and a transfer transistor coupled to the photodiode to transfer the image charge out from the photodiode. The color filter array includes color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the pixels is coupled to a first readout circuit, and the plurality of pixels includes a first subset of the pixels not coupled to a second readout circuit and a second subset of the pixels coupled to the second readout circuit. Two diagonally arranged pixels are coupled together to share a floating diffusion, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.

Abstract: A pixel circuit includes a pixel array and a color filter. The pixel array includes a plurality of pixels arranged in rows and columns, each pixel including four photodiodes, a floating diffusion, and four transfer transistors. The color filter array includes a plurality of color filters each having one of a plurality of colors and disposed over at least one of the pixels. Each of the plurality of pixels is coupled to a first readout circuit, and the plurality of pixels includes (i) a first subset of the pixels not coupled to a second readout circuit and (ii) a second subset of the pixels coupled to the second readout circuit. Floating diffusions of two diagonally arranged pixels are coupled together, and the two diagonally arranged pixels coupled together are disposed underneath color filters of a same color.

Abstract: A local ramp buffer includes a deep N? well layer disposed in a P? substrate beneath a surface of the P? substrate, a P? well disposed between the surface of the P? substrate and the deep N? well layer, and an N? well structure disposed in the P? substrate and coupled to the deep N? well layer. The N? well structure is disposed between the surface of the P? substrate and the deep N? well layer. The P? well is disposed inside an opening in the N? well structure. The N? well structure and the deep N? well layer are configured to isolate the P? well within the opening. A source follower transistor is disposed in the P? well. The source follower transistor includes a gate terminal coupled to the N? well structure and a ramp generator.

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

Abstract: A pixel cell readout circuit comprises a ramp generator having a ramp generator output. A first gain network is coupled to the ramp generator output and configured to provide a first variable comparator gain. A second gain network is coupled to the ramp generator output and configured to provide a second variable comparator gain. A first comparator has a first input coupled to the first gain network. The first comparator further has a second input selectively coupled to a first bitline and selectively coupled to a second bitline. A second comparator has a first input coupled to the second gain network. The second comparator further has a second input selectively coupled to the first bitline and selectively coupled to the second bitline.

Abstract: An imaging system comprises a pixel array configured to generate a plurality of image charge voltage signals in response to incident light, and readout circuitry coupled to the pixel array, the readout circuitry including a plurality of column unit cells. Each column unit cell comprises at least one of a plurality of comparators, wherein each comparator is coupled to receive the ramp signal from the ramp generator through a ramp signal line. Each column unit cell also comprises a compensation current unit coupled to the ramp signal line, each compensation current unit comprising a compensation current source and a compensation current switch coupled to the compensation current source, wherein the compensation current source and the compensation current switch are coupled between a first node on the ramp signal line and a second node.

Abstract: An imaging system comprises a pixel array and readout circuitry coupled to the pixel array. The readout circuitry includes a ramp generator and a plurality of column unit cells, each comprising a column ramp buffer and a column comparator, and each column ramp buffer comprising an input node coupled to receive a ramp signal from the ramp generator, a transistor having a gate terminal coupled to the input node and a drain terminal coupled to a power line, an output node coupled between a source terminal of the transistor and the column comparator, and an alternating current (AC) coupling unit coupled between the input node and the transistor. The AC coupling unit comprises a capacitor coupled between the input node and the gate terminal of the transistor, and a reset switch coupled between the input node and the gate terminal of the transistor.

Abstract: A tail current source of a comparator includes a first transistor and a second transistor configured to operate as current sources, wherein the first and second transistors are coupled between a tail node of the comparator and a voltage node, and wherein the tail comprises a node coupled to first and second inputs of the comparator. The tail current source also includes a switch configured to selectively couple the second transistor between the tail and the voltage node, and a bias voltage source coupled to gates of the first and second transistors. The switch is configured to be on during an analog-to-digital conversion (ADC) reset signal period and an ADC image signal period, and the switch is configured to be off during an auto-zero period, a period between the ADC reset signal and image signal periods, and a period after the ADC image signal period.

Abstract: A readout circuit includes a comparator having a first input coupled to receive a ramp signal from a ramp generator and a second input coupled to receive an analog image data signal from one of a plurality of bitlines. The comparator is configured to generate a comparator output in response to a comparison of the ramp signal and the analog image data signal. A sampling circuit has a first input coupled to receive a sampling control signal and a second input coupled to receive the comparator output. The sampling circuit is configured to generate a sampling output. A counter has a first input coupled to receive a counter control signal and a second input coupled to receive one of the comparator output and a signal from the sampling circuit. The readout circuit is configured to perform correlated multiple sampling (CMS) calculations or non-CMS calculations in response to the sampling output.

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.