Patents by Inventor Hiroaki Fujimoto

Hiroaki Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7625299
    Abstract: A real loft angle of a putter (2) is one to four degrees. In a reference section (D1), an intersection point of a line which passes through a center of gravity (g1) of a head and is perpendicular to a horizontal plane (H1) and a sole surface (18) is represented by (T1), a line passing through the point (T1) and a leading edge point (Le) is represented by (S1), a point which is present on the sole surface (18) and is provided apart from the line (S1) toward a lowermost side is represented by (T2), a line which passes through the point (T2) and is parallel with the line (S1) is represented by (S2), a distance between the point (T2) and the line (S1) is represented by (K1), a line passing through the point (T2) and the point (Le) is represented by (S3), a distance in the front-rear direction between the point (T2) and the point (Le) is represented by (L), and a distance in the front-rear direction between the point (T1) and the point (Le) is represented by (M).
    Type: Grant
    Filed: September 2, 2008
    Date of Patent: December 1, 2009
    Assignee: SRI Sports Limited
    Inventor: Hiroaki Fujimoto
  • Publication number: 20090289357
    Abstract: A semiconductor element includes: a substrate having an integrated circuit; and a wire connection electrode and a bump connection electrode which are provided on a same main surface of the substrate as electrodes having a same connection function to the integrated circuit. The wire connection electrode is provided in a periphery of the main surface. The bump connection electrode is provided inside the wire connection electrode on the main surface. When a straight line dividing the main surface into two regions is determined, the wire connection electrode and the bump connection electrode are located opposite to each other with respect to the straight line.
    Type: Application
    Filed: February 4, 2009
    Publication date: November 26, 2009
    Inventors: Hiroaki FUJIMOTO, Noriyuki NAGAI, Tadaaki MIMURA
  • Publication number: 20090134505
    Abstract: According to the present invention, protrusions 4 are formed on electrodes 3 of semiconductor elements 6, and an optical member 7 is secured on the semiconductor element 6 with an adhesive 8 so as to be pressed onto the protrusions 4.
    Type: Application
    Filed: November 4, 2008
    Publication date: May 28, 2009
    Applicant: Panasonic Corporation
    Inventors: Hiroaki Fujimoto, Yoshihiro Tomita
  • Publication number: 20090130801
    Abstract: There are provided a lead frame including a plurality of first external terminal portions 5 provided on a plane, inner lead portions 6 formed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element 2 flip-chip bonded to the inner lead portions via bumps 3; and an encapsulating resin 4 encapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin.
    Type: Application
    Filed: January 16, 2009
    Publication date: May 21, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Toshiyuki FUKUDA, Masanori MINAMIO, Hiroaki FUJIMOTO, Ryuichi SAHARA, Kenichi ITOU
  • Publication number: 20090111605
    Abstract: A real loft angle of a putter (2) is one to four degrees. In a reference section (D1), an intersection point of a line which passes through a center of gravity (g1) of a head and is perpendicular to a horizontal plane (H1) and a sole surface (18) is represented by (T1), a line passing through the point (T1) and a leading edge point (Le) is represented by (S1), a point which is present on the sole surface (18) and is provided apart from the line (S1) toward a lowermost side is represented by (T2), a line which passes through the point (T2) and is parallel with the line (S1) is represented by (S2), a distance between the point (T2) and the line (S1) is represented by (K1), a line passing through the point (T2) and the point (Le) is represented by (S3), a distance in the front-rear direction between the point (T2) and the point (Le) is represented by (L), and a distance in the front-rear direction between the point (T1) and the point (Le) is represented by (M).
    Type: Application
    Filed: September 2, 2008
    Publication date: April 30, 2009
    Inventor: Hiroaki Fujimoto
  • Patent number: 7495319
    Abstract: There are provided a lead frame including a plurality of first external terminal portions 5 provided on a plane, inner lead portions 6 formed of back surfaces of the respective first external terminal portions and arranged so as to surround a region inside the inner lead portions, and second external terminal portions 7 formed of uppermost surfaces of convex portions positioned outside the respective inner lead portions; a semiconductor element 2 flip-chip bonded to the inner lead portions via bumps 3; and an encapsulating resin 4 encapsulating surroundings of the semiconductor element and the inner lead portions. The first external terminal portions are arranged in a lower surface region of the encapsulating resin along a periphery of the region, and the second external terminal portions are exposed on an upper surface of the encapsulating resin.
    Type: Grant
    Filed: March 3, 2005
    Date of Patent: February 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Toshiyuki Fukuda, Masanori Minamio, Hiroaki Fujimoto, Ryuichi Sahara, Kenichi Itou
  • Patent number: 7495339
    Abstract: There is provided a connection structure between a Si electrode (Si member) and an Al wire (Al member). Between the Si electrode and the Al wire, a first part and second parts are present in interposed relation. Each of the first and second parts is in contact with the Si electrode and with the Al wire. In the first part, a Si oxide layer and an Al oxide layer are present. The Si oxide layer is in contact with the Si electrode. The Al oxide layer is interposed between the Si oxide layer and the Al wire. In some of the second parts, Al is present. In the others of the second parts, a Si portion and an Al portion are present.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: February 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Masanori Minamio, Hiroaki Fujimoto, Atsuhito Mizutani, Hisaki Fujitani, Toshiyuki Fukuda
  • Publication number: 20090039509
    Abstract: A semiconductor device is provided which can prevent contacts between thin metal wires for electrically connecting the electrodes of a substrate with the electrodes of a semiconductor element. The semiconductor device of the present invention includes metal protrusions formed on the electrodes of the semiconductor element, the metal protrusions having lower hardness than the hardness of the thin metal wires. The metal protrusions are bonded to the thin metal wires.
    Type: Application
    Filed: August 5, 2008
    Publication date: February 12, 2009
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Manabu Tanabe, Hiroaki Fujimoto
  • Publication number: 20080311326
    Abstract: A method for producing a tubular body includes a step of winding at least one of winding bias prepregs, at least one of straight prepregs, and at least one of hoop prepregs round a core. At the winding step, after the hoop prepreg and/or the hoop prepreg are adherently layered in advance on a base prepreg consisting of the bias prepreg or the straight prepreg to form a laminate and/or a laminate, the laminate and/or the laminate are wound on the core so that the hoop prepreg and/or the hoop prepreg are wound on the core integrally with the base prepreg or the base prepreg.
    Type: Application
    Filed: March 14, 2008
    Publication date: December 18, 2008
    Inventor: Hiroaki Fujimoto
  • Publication number: 20080179711
    Abstract: According to the present invention, a plurality of semiconductor devices having semiconductor chips 13 molded on a semiconductor package substrate 1 by a molding resin 15 can be manufactured by forming recesses 10 around each semiconductor package substrate 1 composing a substrate 8 for a BGA package, and in the state where a molding resin 15 is filled on the substrate 8 including the recesses 10 for resin molding, cutting the substrate 8 and the molding resin 15 along partition lines 9.
    Type: Application
    Filed: November 9, 2007
    Publication date: July 31, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Kenichi Imazu
  • Patent number: 7366593
    Abstract: A movable object maneuver method wherein a destination point is set; wherein a thrust value is calculated in real time which minimizes or maximizes a performance index associated with one or more state variables and thrust required for a movable object to reach the destination point and which takes into account non-linear conditions inherent to the movable object; and wherein the movable object is moved based on the calculated thrust value.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: April 29, 2008
    Assignees: Kawasaki Jukogyo Kabushiki Kaisha, Kabushiki Kaisha Kawasaki Zosen
    Inventors: Hiroaki Fujimoto, Yukinobu Kohno, Masaaki Higashi, Masanori Hamamatsu, Kenichi Nakashima, Yasuo Saito, Hiroshi Ohnishi
  • Publication number: 20080083964
    Abstract: A semiconductor image sensor die includes a substrate, an imaging area, a surrounding circuit area, a plurality of electrode portions, a translucent member, a transparent adhesive, and a bump. The imaging area, the surrounding circuit area, and the electrode portion are provided on an upper surface of the substrate. The surrounding circuit area is provided outside the imaging area. The electrode portion is provided outside the surrounding circuit area. The translucent member is adhered via the transparent adhesive to the imaging area, covering the imaging area. The bump is provided on a portion of the electrode portions. The surface of the bump includes an upper surface which is located higher than an upper surface of the transparent adhesive.
    Type: Application
    Filed: August 15, 2007
    Publication date: April 10, 2008
    Inventors: Hiroaki Fujimoto, Masanori Minamio, Toshiyuki Fukuda
  • Publication number: 20080073786
    Abstract: In a semiconductor device of the present invention, of wires 5a, 5b and 5c which are vertically arranged to connect a plurality of electrodes 3 formed on a major surface of a semiconductor chip 2 and internal electrodes 4 of conductor portions arranged around the semiconductor chip 2, the wires 5a at the lowest level have the lowest stiffness and the wires 5b and 5c at a higher level have higher stiffness. With this configuration, it is possible to eliminate contact among the wires 5a, 5b and 5c, thereby improving the yields.
    Type: Application
    Filed: September 21, 2007
    Publication date: March 27, 2008
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Manabu Tanabe, Hiroaki Fujimoto
  • Patent number: 7309624
    Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: December 18, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
  • Patent number: 7286729
    Abstract: An optical device cavity structure includes: insulator layers and metal layers alternately layered on one another; a first terminal section which is formed on a mounting surface to be mounted on a wiring substrate and which is electrically connected to the wiring substrate; a cavity portion having a generally rectangular opening formed in a central portion of the upper surface; and a light-transmitting member placement section formed on the upper surface surrounding the opening for receiving a light-transmitting member thereon, wherein the light-transmitting member is for transmitting therethrough light to be received by, or light emitted from, an optical element chip.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: October 23, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masanori Minamio, Toshiyuki Fukuda, Noriyuki Yoshikawa, Hiroaki Fujimoto, Yoshinobu Kunitomo
  • Publication number: 20070187834
    Abstract: There is provided a connection structure between a Si electrode (Si member) and an Al wire (Al member). Between the Si electrode and the Al wire, a first part and second parts are present in interposed relation. Each of the first and second parts is in contact with the Si electrode and with the Al wire. In the first part, a Si oxide layer and an Al oxide layer are present. The Si oxide layer is in contact with the Si electrode. The Al oxide layer is interposed between the Si oxide layer and the Al wire. In some of the second parts, Al is present. In the others of the second parts, a Si portion and an Al portion are present.
    Type: Application
    Filed: October 10, 2006
    Publication date: August 16, 2007
    Inventors: Masanori Minamio, Hiroaki Fujimoto, Atsuhito Mizutani, Hisaki Fujitani, Toshiyuki Fukuda
  • Publication number: 20070035035
    Abstract: An aluminum wire is bonded to a silicon electrode by a wedge tool pressing the aluminum wire against the silicon electrode. In this way, a firmly bonded structure is obtained by sequentially stacking aluminum, aluminum oxide, silicon oxide, and silicon.
    Type: Application
    Filed: July 24, 2006
    Publication date: February 15, 2007
    Inventors: Masanori Minamio, Hiroaki Fujimoto, Atsuhito Mizutani, Hisaki Fujitani, Toshiyuki Fukuda
  • Publication number: 20060252183
    Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.
    Type: Application
    Filed: July 12, 2006
    Publication date: November 9, 2006
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
  • Patent number: 7125751
    Abstract: Disclosed is a semiconductor device which comprises a semiconductor element having a plurality of electrodes, a plurality of external electrodes disposed around the periphery of the semiconductor element, a fine wire electrically connected between at least one of surfaces of each of the plural external electrodes and at least one of the plural electrodes of the semiconductor element, and an encapsulating resin which encapsulates the semiconductor element, the plural external electrodes, and the fine wires and whose external shape is a rectangular parallelepiped, wherein a bottom surface of the semiconductor element and a bottom surface of each of the plural external electrode are exposed from a bottom surface of the encapsulating resin and a top surface of the semiconductor element and a top surface of each of the plural external electrode are located substantially coplanar with each other.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: October 24, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroaki Fujimoto, Tsuyoshi Hamatani, Toru Nomura
  • Publication number: 20060222285
    Abstract: An optical device cavity structure includes: insulator layers and metal layers alternately layered on one another; a first terminal section which is formed on a mounting surface to be mounted on a wiring substrate and which is electrically connected to the wiring substrate; a cavity portion having a generally rectangular opening formed in a central portion of the upper surface; and a light-transmitting member placement section formed on the upper surface surrounding the opening for receiving a light-transmitting member thereon, wherein the light-transmitting member is for transmitting therethrough light to be received by, or light emitted from, an optical element chip.
    Type: Application
    Filed: April 4, 2006
    Publication date: October 5, 2006
    Inventors: Masanori Minamio, Toshiyuki Fukuda, Noriyuki Yoshikawa, Hiroaki Fujimoto, Yoshinobu Kunitomo