Patents by Inventor Hiroaki Ikeda

Hiroaki Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130298730
    Abstract: A composite soft magnetic material having low magnetostriction and high magnetic flux density contains: pure iron-based composite soft magnetic powder particles that are subjected to an insulating treatment by a Mg-containing insulating film or a phosphate film; and Fe—Si alloy powder particles including 11%-16% by mass of Si. A ratio of an amount of the Fe—Si alloy powder particles to a total amount is in a range of 10%-60% by mass. A method for producing the composite soft magnetic material comprises the steps of: mixing a pure iron-based composite soft magnetic powder, and the Fe—Si alloy powder in such a manner that a ratio of the Fe—Si alloy powder to a total amount is in a range of 10%-60%; subjecting a resultant mixture to compression molding; and subjecting a resultant molded body to a baking treatment in a non-oxidizing atmosphere.
    Type: Application
    Filed: February 22, 2012
    Publication date: November 14, 2013
    Applicants: DIAMET CORPORATION, MITSUBISHI MATERIALS CORPORATION
    Inventors: Hiroaki Ikeda, Hiroshi Tanaka, Kazunori Igarashi
  • Publication number: 20130242318
    Abstract: In the invention, an inclination amount of sensors is reflected in positional deviation correction patterns, and for correcting formation positions of images of various colors, the positional deviation correction patterns are formed on a conveying belt. The positional deviation correction patterns are detected by the sensors. A control unit calculates positional deviation correction amounts based on detection results of the positional deviation correction patterns. Based on the calculated positional deviation correction amounts, the control unit performs calculation for correcting the positional deviation correction patterns, and cancels the inclination amount reflected in the calculation results to obtain final positional deviation correction amounts. Skew correction is performed based on the final positional deviation correction amounts, and thus, the positional deviations are corrected.
    Type: Application
    Filed: March 1, 2013
    Publication date: September 19, 2013
    Inventors: Akinori YAMAGUCHI, Masayuki HAYASHI, Hiroaki IKEDA, Kunihiro KOMAI, Tatsuya MIYADERA, Takeshi SHIKAMA, Takuhei YOKOYAMA, Yoshinori SHIRASAKI, Motohiro KAWANABE
  • Publication number: 20130213091
    Abstract: In a method of manufacturing a glass substrate for an information recording medium including a step for chemically strengthening the glass substrate by contacting the glass substrate with chemical strengthening processing liquid containing chemical strengthening salt, concentration of Fe and Cr is 500 ppb or less in said chemical strengthening salt, respectively. The concentration may be detected by the use of an ICP (Inductively Coupled Plasma) emission spectrometry analyzing method or a fluorescent X-ray spectroscopy analyzing method.
    Type: Application
    Filed: March 18, 2013
    Publication date: August 22, 2013
    Inventors: Hiroaki IKEDA, Masaru Suzuki, Kazuna Sasaki, Yumi Mukai, Jun Ozawa
  • Patent number: 8513121
    Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.
    Type: Grant
    Filed: September 15, 2012
    Date of Patent: August 20, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
  • Publication number: 20130207339
    Abstract: According to an embodiment, provided is an image forming device that includes: an image forming unit forming an image in a predetermined cycle in a direction orthogonal to a conveying direction of a printing medium; a velocity acquisition unit acquiring a conveying velocity of the printing medium at a position where the image is formed by the image forming unit; and a correcting unit correcting the cycle on which the image forming unit forms the image in accordance with the conveying velocity acquired by the velocity acquisition unit.
    Type: Application
    Filed: February 7, 2013
    Publication date: August 15, 2013
    Inventors: Takuhei YOKOYAMA, Yoshinori SHIRASAKI, Tatsuya MIYADERA, Masayuki HAYASHI, Kunihiro KOMAI, Motohiro KAWANABE, Hiroaki IKEDA, Takeshi SHIKAMA, Akinori YAMAGUCHI
  • Patent number: 8420154
    Abstract: In a method of manufacturing a glass substrate for an information recording medium including a step for chemically strengthening the glass substrate by contacting the glass substrate with chemical strengthening processing liquid containing chemical strengthening salt, concentration of Fe and Cr is 500 ppb or less in said chemical strengthening salt, respectively. The concentration may be detected by the use of an ICP (Inductively Coupled Plasma) emission spectrometry analyzing method or a fluorescent X-ray spectroscopy analyzing method.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: April 16, 2013
    Assignee: Hoya Corporation
    Inventors: Hiroaki Ikeda, Masaru Suzuki, Kazuna Sasaki, Yumi Mukai, Jun Ozawa
  • Publication number: 20130084109
    Abstract: An image forming apparatus can transfer a plurality of color component images onto a surface of a recording medium to form an image on the recording medium. The image forming apparatus includes a pattern generation part to generate information about an alignment pattern to be used for a calibration of an image forming, a plurality of stations each including a photosensitive drum to form an alignment pattern corresponding to each of a plurality of color components onto a carry belt or the recording medium, and a read part to detect a plurality of alignment patterns formed by the plurality of stations.
    Type: Application
    Filed: October 3, 2012
    Publication date: April 4, 2013
    Inventors: Takeshi SHIKAMA, Masayuki HAYASHI, Kunihiro KOMAI, Tatsuya MIYADERA, Motohiro KAWANABE, Yoshinori SHIRASAKI, Hiroaki IKEDA, Akinori YAMAGUCHI, Takuhei YOKOYAMA
  • Publication number: 20130070040
    Abstract: An exposure control apparatus includes: a plurality of line memories; a processing unit that processes image data by successively recording the image data to the plurality of line memories, and successively reading the image data from the plurality of line memories; and an exposing unit that performs, with an exposure cycle, an exposure process according to the processed image data, and that forms a latent image based on the image data onto an image carrier, wherein the image data is transferred with a cycle which is N times as high as the exposure cycle (N is a natural number), and the processing unit reads the image data N times with the exposure cycle.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 21, 2013
    Inventors: Tatsuya Miyadera, Yoshinori Shirasaki, Motoyoshi Takahashi, Masayuki Hayashi, Kunihiro Komai, Fuminori Tsuchiya, Akinori Yamaguchi, Hiroaki Ikeda
  • Publication number: 20130071130
    Abstract: A toner consumption calculator includes a plurality of line memories; a recorder that sequentially records image data including a plurality of pixels into the line memories; a skew correction unit that performs skew correction on the image data by sequentially reading the image data from the line memories while controlling read timing; and a counter that sequentially reads the image data from the line memories and counts toner consumption of a target pixel on the basis of light amounts of surrounding pixels of the target pixel.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 21, 2013
    Inventors: Masayuki HAYASHI, Yoshinori Shirasaki, Kunihiro Komai, Hiroaki Ikeda, Motoyoshi Takahashi, Fuminori Tsuchiya, Akinori Yamaguchi, Tatsuya Miyadera, Motohiro Kawanabe, Yasuo Yamaguchi
  • Publication number: 20130063536
    Abstract: A light source control apparatus which controls, based on image data input, light emission of a light source which forms an electrostatic latent image on an image bearing body in an electrophotographic image forming apparatus is disclosed, including a pattern generating unit which generates an internal pattern for position aligning and concentration correcting according to the image data; and a mirroring processing unit which performs a process of mirroring the image data and the internal pattern at a later stage of the pattern generating unit.
    Type: Application
    Filed: August 24, 2012
    Publication date: March 14, 2013
    Inventors: Kunihiro KOMAI, Masayuki Hayashi, Hiroaki Ikeda, Takeshi Shikama, Akinori Yamaguchi, Tatsuya Miyadera, Motohiro Kawanabe, Yoshinori Shirasaki, Takuhei Yokoyama
  • Publication number: 20130044176
    Abstract: An optical writing device forms an electrostatic latent image and includes a pixel-information acquiring unit that acquires pixel information and stores the acquired pixel information in a storage medium with respect to each main scanning line; a tilt correcting unit that generates a tilt correction signal specifying a main scanning line from which the pixel information to be input to a light source is read out from the storage medium in order to correct a tilt of the electrostatic latent image; a position correcting unit that generates a position correction signal specifying a timing to input the pixel information to the light source in order to correct a position of the electrostatic latent image; and a pixel-information-input control unit that controls input of the pixel information from the storage medium to the light source in response to the tilt correction signal and the position correction signal.
    Type: Application
    Filed: August 13, 2012
    Publication date: February 21, 2013
    Inventors: Yoshinori Shirasaki, Masayuki Hayashi, Yasuo Yamaguchi, Kunihiro Komai, Tatsuya Miyadera, Motohiro Kawanabe, Hiroaki Ikeda, Akinori Yamaguchi, Fuminori Tsuchiya, Motoyoshi Takahashi
  • Patent number: 8373210
    Abstract: A semiconductor device includes a pair of electromagnetically coupled inductors. Each of the inductors is comprised of a plurality of through electrodes which extend through a semiconductor substrate, and wires which connect the plurality of through electrodes in series.
    Type: Grant
    Filed: April 7, 2010
    Date of Patent: February 12, 2013
    Assignee: Elpida Memory, Inc.
    Inventors: Hiroaki Ikeda, Mitsuru Shiozaki, Atsushi Iwata
  • Patent number: 8358375
    Abstract: To solve the problems in the prior art, the present invention provides a method for measuring a time difference between digital video signals and digital audio signals, wherein said method comprises the steps of extracting respective time series data from respective frequency domains of said digital video signals and said digital audio signals; statistically identifying the cross-correlation of said time series data in said frequency domains, thereby measuring the time difference between said digital video signals and said digital audio signals.
    Type: Grant
    Filed: October 6, 2006
    Date of Patent: January 22, 2013
    Assignee: National University Corporation Chiba University
    Inventors: Hiroaki Ikeda, Reiko Iwai
  • Publication number: 20130011967
    Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.
    Type: Application
    Filed: September 15, 2012
    Publication date: January 10, 2013
    Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
  • Patent number: 8334465
    Abstract: A wafer (or a circuit board), which is used to perform three-dimensional mounting, has protrusion 20 which is provided in low melting point metal 15 for electrically connecting mutually joined wafers 61 and 62, and which defines an interval between mutually joined wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted. A joining structure of wafers 61 and 62 is manufactured by using wafers 61 and 62, at least one of which has protrusion 20. In the manufactured joining structure of wafers 61 and 62, wafers 61 and 62 are electrically connected to each other by low melting point metal 15, and protrusion 20, which defines the interval between wafers 61 and 62 without being deformed at the time when low melting point metal 15 is melted, is provided in low melting point metal 15.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: December 18, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Masakazu Ishino, Hiroaki Ikeda, Hideharu Miyake, Shiro Uchiyama, Hiroyuki Tenmei, Kunihiko Nishi, Yasuhiro Naka, Nae Hisano
  • Patent number: 8315331
    Abstract: A transmission method for transmitting transmission data via a single line, includes: transmitting, as the transmission data, data that has one rising or falling transition of the amplitude of the data in each clock cycle of a clock and that carries a 2- or greater-bit value, making use of the phase from the edge of the clock to the transition in amplitude of the data.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: November 20, 2012
    Assignees: NEC Corporation, Elpida Memory, Inc.
    Inventors: Hideaki Saito, Hiroaki Ikeda
  • Publication number: 20120287479
    Abstract: In an optical scanner, when an emission control unit varies a period at which image data is output from an output buffer of the emission control unit in order to correct a sub scan magnification of a LED array and a vacant region of an input buffer of the emission control unit ceases to exist, a buffer control unit temporarily stores the image data in a vacant region of a memory of an image correcting unit, and transfers the image data temporarily stored in the memory to the input buffer when the vacant region is generated in the input buffer.
    Type: Application
    Filed: May 2, 2012
    Publication date: November 15, 2012
    Applicant: RICOH COMPANY, LTD.
    Inventors: Motoyoshi TAKAHASHI, Masayuki HAYASHI, Hiroaki IKEDA, Kunihiro KOMAI, Yoshinori SHIRASAKI, Fuminori TSUCHIYA, Akinori YAMAGUCHI, Tatsuya MIYADERA
  • Patent number: 8305627
    Abstract: A pattern image of either a registration correction pattern including a plurality of position detecting marks or a misregistration correction performing determination pattern having a plurality of position detecting marks, the number of which marks is smaller than that of the registration correction pattern image is formed. A misregistration amount is calculated based on an image formed position detected with the use of the pattern image. It is determined whether the registration correction is to be carried out, based on the misregistration amount with the use of an image formed position of the correction performing determination pattern. When it is determined to carry out the misregistration correction, the misregistration correction is carried out based on the misregistration amount with the use of image formed positions of the misregistration correction pattern.
    Type: Grant
    Filed: February 23, 2009
    Date of Patent: November 6, 2012
    Assignee: Ricoh Company, Ltd.
    Inventor: Hiroaki Ikeda
  • Patent number: 8298940
    Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.
    Type: Grant
    Filed: January 12, 2011
    Date of Patent: October 30, 2012
    Assignee: Elpida Memory, Inc.
    Inventors: Masakazu Ishino, Hiroaki Ikeda, Kayoko Shibata
  • Publication number: 20120262974
    Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.
    Type: Application
    Filed: June 28, 2012
    Publication date: October 18, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventors: Yoshinori MATSUI, Toshio SUGANO, Hiroaki IKEDA