Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: A semiconductor device includes a semiconductor chip having first and second surfaces. A first through electrode extends through the semiconductor chip. A first surface electrode is positioned on the first surface of the semiconductor chip and coupled to a first end of the first through electrode. A second surface electrode is positioned on the second surface of the semiconductor chip. The second surface electrode is coupled to a second end of the first through electrode. A second through electrode extends through the semiconductor chip and has third and fourth ends. A third surface electrode is positioned on the second surface of the semiconductor chip and is coupled to the fourth end of the second through electrode. The semiconductor device is free of a surface electrode on the first surface of the semiconductor chip and is coupled to the third end of the second through electrode.

Abstract: A positional error detection method forms, on a belt which is transported in a transport direction, positional error detection marks for detecting a positional error between image positions of first and second colors, detects the positional error detection marks on the belt, and computes the positional error based on the detected positional error detection marks. The positional error detection marks include first and second marks which are inclined in mutually opposite directions with respect to the transport direction, and third marks which are perpendicular to the transport direction.

Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

Abstract: A data transfer method is disclosed in a multi-chip semiconductor device which comprises a plurality of inter-chip wires. First, a test is conducted to determine whether or not each inter-chip wire is capable of normally transferring data, on circuits arranged on chips between which the inter-chip wire is connected. When an inter-chip wire incapable of normally transferring data exists, the data transfer speed of the buffer circuit that is on the chip on the transmission and that is connected to an inter-chip wire capable of normally transferring data is increased. The buffer circuit, whose data transfer speed has been increased, transfers data which would otherwise be transferred through the inter-chip wire incapable of normally transferring data, together with the data which should be transferred thereby, to the chip on the reception side chip through an inter-chip wire connected to the buffer circuit at the data transfer speed.

Abstract: A liquid crystal display device having a liquid crystal panel includes a common voltage generating section (5) that supplies a common voltage to a common electrode connected in common to a plurality of liquid crystal cells that comprise said liquid crystal panel (13); a liquid crystal driving section (12) that supplies a voltage corresponding to an input image signal to said plurality of liquid crystal cells so as to display an image based on said input image signal on said liquid crystal panel (13); and a controlling section (10) that causes said common voltage generating section (15) to change a value of the common voltage generated thereby to correspond to a signal that represents an amount of light that enters said liquid crystal panel.

Abstract: The present invention is aimed at appropriately suppressing display failure such as a tailing phenomenon and the like in a normally white type liquid crystal panel. A driver (3) supplies a drive voltage in conformity with an image signal received by an image signal processing circuit (1), to a liquid crystal panel (4). A histogram detector (5) detects a histogram representing the relationship between the signal level of the image signal received by the image signal processing circuit (1) and the number of pixels. A CPU (6) calculates, based on the histogram detected by the histogram detector (5), a first proportion of the number of pixels (on the white side) whose signal level is equal to or greater than a first defined value, to the total number of pixels of the histogram and a second proportion of the number of pixels (on the black side) whose signal level is equal to or smaller than a second defined value that is smaller than the first defined value, to the total number of pixels of the histogram.

Abstract: Disclosed is a method for enhancing the function of a T cell, which is characterized by inhibiting the expression of programmed death-1 ligand 1 (PD-L1) and/or programmed death-1 ligand 2 (PD-L2) in the T cell. Also disclosed is a function-enhanced T cell which is produced by the function enhancement method. Further disclosed is a therapeutic agent comprising the function-enhanced T cell. The T cell can enhance an immune response to cancer, and is useful in an immunotherapy effective for cancer and the treatment or prevention of infectious diseases and autoimmune diseases.

Abstract: A stacked semiconductor memory device includes an interface chip and a plurality of core chips, in which the interface chip and the plurality of core chips are stacked. The core chips are mutually connected by a plurality of data through electrodes. The core chips each include a plurality of memory arrays. In response to an access request, the plurality of memory arrays corresponding to a predetermined data through electrode are activated, and the plurality of activated memory arrays and the predetermined data through electrode are sequentially connected. Thereby, even though it requires approximately ten-odd ns for transferring the first data, similarly to the conventional case, it is possible to transfer the subsequent data at high speed determined by the reaction rate (1 to 2 ns) of the through electrode. As a result, it becomes possible to increase a bandwidth while suppressing the number of through electrodes.

Abstract: A stacked type semiconductor memory device of having a structure in which a plurality of semiconductor chips is stacked and a desired semiconductor chip can be selected by assigning a plurality of chip identification numbers different from each other are individually assigned to the plurality of semiconductor chips comprising: a plurality of operation circuits which is connected in cascade in a stacking order of the plurality of semiconductor chips and outputs the plurality of identification numbers different from each other by performing a predetermined operation; and a plurality of comparison circuits which detects whether or not each the identification number and a chip selection address commonly connected to each the semiconductor chip are equal to each other by comparing them.

Abstract: The lithium secondary battery provided by the present invention includes an electrode provided with an insulating particle-containing layer (34) having a configuration in which an active material layer (344) is retained on a current collector (342), and an insulating particle-containing layer (346), containing insulating particles (44) and a binder (46), is provided on the active material layer (344). A portion (346A) of the insulating particle-containing layer (346) facing the active material layer contains the binder (46) at a higher weight content than a portion (346B) facing an outer surface thereof.

Abstract: Disclosed are: a cell capable of expressing an exogenous GITRL or an exogenous GITRL derivative; a method for producing the cell; a therapeutic or prophylactic agent comprising the cell as an active ingredient; use of the cell in the manufacture of a therapeutic or prophylactic agent; a method comprising a step of administering the cell to a subject; a viral vector carrying a gene encoding a GITRL or a GITRL derivative; a therapeutic or prophylactic agent comprising the viral vector as an active ingredient; use of the viral vector in the manufacture of a therapeutic or prophylactic agent; and a method comprising a step of administering the viral vector to a subject.

Abstract: A method of manufacturing a semiconductor device includes: supplying a supercritical fluid mixed with an under-fill material to a stacked unit, which has a plurality of stacked semiconductor chips; and filling the under-fill material in the space between the plurality of the semiconductor chips, by heating the stacked unit placed in the inside of the high-pressure vessel and curing the under-fill material flowing in the space between the plurality of the semiconductor chips by a polymerization reaction, while the supercritical fluid is being supplied.

Abstract: A method is provided for manufacturing an electrode that has a porous inorganic layer on the surface of an active material layer and is suitable for constructing a nonaqueous secondary battery with excellent input-output performance. In this manufacturing method, an electrode perform, which has an active material layer (344) consisting primarily of active material particles (42) and supported on a collector (342), is prepared. The water concentration of at least the surface (344a) of the active material layer (344) is adjusted to 100 ppm to 500 ppm. A slurry (S) containing inorganic particles (44), a binder and an organic solvent is coated on the surface (344a) of the active material layer with the water concentration thus adjusted, to form a porous inorganic layer.

Abstract: An image display apparatus includes: a panel (16a) that includes a plurality of picture elements that change transmittance of light according to picture levels; a detection unit (12) that detects, in one-image portions of the panel (16a), picture levels for each of the plurality of picture elements from picture signals that indicate the picture levels of each picture element; and a processor (18) that, based on the picture levels of one-image portions that were detected by the detection unit (12), adjusts the transmittance of light of the plurality of picture elements such that the image realized by the picture signal is brighter when a value that corresponds to brightness is greater than a predetermined threshold value.

Abstract: A lithium secondary battery provided by the present invention includes an electrode body (80) having a structure in which a positive electrode (10) and a negative electrode (20) are laminated, with a separator (30) interposed therebetween, and a porous insulating layer (40) obtained by filling and molding insulating particles is formed on the surface of at least one of the positive electrode (10) and the negative electrode (20) on the side facing the separator (30), wherein insulating particles having a tap density of 0.4 g/cm3 to 0.9 g/cm3 are used as the insulating particles that compose the porous insulating layer (40), and moreover a pressure (90) that is applied in the direction of the lamination to the electrode body (80) is set to a range of 4 kgf/cm2 to 50 kgf/cm2.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: In a lithium secondary battery provided by the present invention, the layer density on a side facing a protective layer (46) in a negative electrode active material layer (44) and/or positive electrode active material layer where the protective layer is formed, the protective layer containing an insulating filler and a binder, is higher than the layer density in a central portion and a side facing a current collector (42) in the negative electrode active material layer and/or positive electrode active material layer where the protective layer is formed.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.