Abstract: A semiconductor device comprises a mounting substrate, a semiconductor element provided above said mounting substrate, a package substrate provided above said mounting substrate with said semiconductor element therebetween and electrically connected to said semiconductor element via a primary connecting bump, a liquid cooling module cooling said semiconductor element by a liquid refrigerant, in which a heat receiving section of the liquid cooling module is disposed between said semiconductor element and said mounting substrate, and a plurality of secondary connecting bumps provided between said package substrate and said mounting substrate.

Abstract: A semiconductor device comprising a plurality of semiconductor chips and a plurality of through-line groups is disclosed. Each of the through-line groups consists of a unique number of through-lines. The numbers associated with the through-line groups are mutually coprime to each other. When one of the through-lines is selected for the each through-line group, one of the semiconductor chip is designated by a combination of the selected through-lines of the plurality of the through-line groups.

Abstract: A first correction pattern and a second correction pattern are formed on an endless conveyor belt. The first correction pattern is located ahead of the second correction pattern on the conveyor belt with respect to the direction of movement of the conveyor belt. A sensor detects positional information of the correction patterns. A timing changing unit (controlling unit) changes a detection timing of the second correction pattern from a time point at which the sensor detects the second correction pattern.

Abstract: To solve the problems in the prior art, the present invention provides a method for measuring a time difference between digital video signals and digital audio signals, wherein said method comprises the steps of extracting respective time series data from respective frequency domains of said digital video signals and said digital audio signals; statistically identifying the cross-correlation of said time series data in said frequency domains, thereby measuring the time difference between said digital video signals and said digital audio signals.

Abstract: A method of manufacturing an electrode active material particle for a rechargeable battery wherein a layer of an active material capable of being alloyed with Li is formed on a surface of a metal particle incapable of being alloyed with Li and then a heat treatment is conducted to diffuse the active material into the metal particle so that the resulting active material particle has a concentration profile in which a concentration of a metal element of the metal particle decreases from an interior toward the surface.

Abstract: A memory module of the present invention has a memory core chip for storing information, an interface chip for controlling data input/output, an interposer chip for transmitting/receiving data to/from the outside, and an external connection terminal provided in closest proximity to the interposer chip. A heat dissipating plate is provided in closest proximity to the interface chip. The interposer chip has a substrate made of a semiconductor material that is similar to the memory core chip, a land for holding the external connection terminal, a wire connected to the external connection terminal, and an insulating film for insulating the wire. The land, wire, and insulating film are integrally formed on one surface of the interposer chip.

Abstract: A liquid crystal display apparatus includes common voltage generator circuit (5) for supplying a common voltage to a common electrode connected in common to a plurality of liquid crystal cells which form part of liquid crystal panel (9); liquid crystal driving circuit (2) for inversely driving liquid crystal panel (9); timer (8) for measuring a time for which liquid crystal panel 9 has been used; storage unit (10) for storing characteristic data which represents the relationship between used hours of liquid crystal panel (9) and an optimal value for the common voltage; and control unit (4) for determining a time for which liquid crystal panel (9) has been used up to the present time based on a measurement result by timer (8), retrieving an optimal value for the common voltage for the determined used time with reference to the characteristic data stored in storage unit (10), and controlling such that a magnitude of the common voltage output from the common voltage generator circuit is equal to the optimal valu

Abstract: A wire embedded in a semiconductor substrate is covered with an insulating film, and a bias voltage is applied to the semiconductor substrate or to the wire to form a depletion layer extending from an edge of the insulating film. Alternatively, a semiconductor layer having a different conductivity type from the semiconductor substrate is formed within the semiconductor substrate to surround the insulating film.

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: The similarity between a search form and a registered form is calculated on a page-by-page basis in a predetermined order. Every time the page similarity is calculated, it is determined whether or not a value representing the similarity is smaller than a predetermined threshold value. If it is determined that the similarity value is smaller than the threshold value, the registered form is removed, at this point, from candidates for a recognition target. A form having a possibility of page repetition can also be recognized.

Abstract: A bonding method (three-dimensional mounting) of semiconductor substrates is provided to sequentially bond a principal surface of a silicon wafer on which coupling bumps are formed, and a principal surface of the other silicon wafer on which pads are formed, by an adhesive applied to at least one of the principal surfaces. However, there is a problem of poor electrical coupling due to displacement of the bumps and the pads when bonded together. The present invention solves such a problem by conducting temporary positioning of the silicon wafers, adjusting the positions of the coupling bumps and pads while confirming the positions by a method such as x-ray capable of passing through the silicon wafers, and bonding the bumps and the pads together while hardening an interlayer adhesive provided between the principal surfaces of the silicon wafers by thermocompression.

Abstract: A transmission method for transmitting transmission data via a single line, includes: transmitting, as the transmission data, data that has one rising or falling transition of the amplitude of the data in each clock cycle of a clock and that carries a 2- or greater-bit value, making use of the phase from the edge of the clock to the transition in amplitude of the data.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: A pattern image of either a registration correction pattern including a plurality of position detecting marks or a misregistration correction performing determination pattern having a plurality of position detecting marks, the number of which marks is smaller than that of the registration correction pattern image is formed. A misregistration amount is calculated based on an image formed position detected with the use of the pattern image. It is determined whether the registration correction is to be carried out, based on the misregistration amount with the use of an image formed position of the correction performing determination pattern. When it is determined to carry out the misregistration correction, the misregistration correction is carried out based on the misregistration amount with the use of image formed positions of the misregistration correction pattern.

Abstract: A semiconductor memory device has a plurality of core chips and an interface chip, whose specification can be easily changed, while suppressing the degradation of its reliability. The device has an interposer chip. First internal electrodes connected to core chips are formed on the first surface of the interposer chip. Second internal electrodes connected to an interface chip and third internal electrodes connected to external electrodes are formed on the second surface of the interposer chip. The interface chip can be mounted on the second surface of the interposer chip whenever desired. Therefore, the memory device can have any specification desirable to a customer, only if an appropriate interface chip is mounted on the interposer chip, as is demanded by the customer. Thus, the core chips do not need to be stocked in great quantities in the form of bare chips.

Abstract: A memory module of the present invention is provided with a memory core chip that is placed between an interface chip and an interposer chip and has a relay wire for electrically connecting these chips, an interposer chip that transmits type-information, that is information showing the type of the memory core chip, to the interface chip through the relay wire, and the interface chip that controls the memory core chip in accordance with the type-information received from the interposer chip.

Abstract: A stacked memory is configured such that a ratio between data and ECC bits, a ratio between quantities of data layers and ECC layers, and a ratio between quantities of data activated mats and ECC activated mats are equal to each other. The memory chip has a greater quantity of mats than the quantity of stacked layers. The stacked memory is thus allowed to establish a desired ratio between the quantities of data bits and ECC bits.

Abstract: A positional error detection method forms, on a belt which is transported in a transport direction, positional error detection marks for detecting a positional error between image positions of first and second colors, detects the positional error detection marks on the belt, and computes the positional error based on the detected positional error detection marks. The positional error detection marks include first and second marks which are inclined in mutually opposite directions with respect to the transport direction, and third marks which are perpendicular to the transport direction.

Abstract: In a memory module including a plurality of DRAM chips which transmit/receive a system data signal with a predetermined data width and at a transfer rate and which transmit/receive an internal data signal having a larger data width and a lower transfer rate as compared with the system data signal, the transfer rate of the system data signal is restricted. Current consumption in DRAMs constituting the memory module is large, hindering speed increases. For this memory module, a plurality of DRAM chips are stacked on an IO chip. Each DRAM chip is connected to the IO chip by a through electrode, and includes a constitution for mutually converting the system data signal and the internal data signal in each DRAM chip by the IO chip. Therefore, wiring between the DRAM chips can be shortened, and DLL having a large current consumption may be disposed only on the IO chip.

Abstract: Data transfer speed is increased in a semiconductor storage device in which the core unit and the interface unit are separate chips. The device has a plurality of core chips through in which a memory cell is formed, and an interface chip in which a peripheral circuit is formed for the memory cell. The plurality of core chips through have latch circuit units through for temporarily storing data to be outputted by the memory cell, and latch circuit units through for temporarily storing data to be inputted to the memory cell, respectively, and these latch circuit units through and latch circuit units through are connected in a cascade to the interface chip. Since the plurality of latch circuit units connected in a cascade can thereby perform a pipeline operation, it becomes possible to achieve high-speed data transfer.